MAX6366 View Datasheet(PDF) - Maxim Integrated

Part Name

Description

MFG CO.

MAX6366

SOT23 / Low-Power P Supervisory Circuits with Battery Backup and Chip-Enable Gating

Maxim Integrated 

SOT23, Low-Power µP Supervisory Circuits

with Battery Backup and Chip-Enable Gating

OUT goes high and stays high regardless of any sub-

sequent transitions on CE IN during the reset event.

When CE OUT is disconnected from CE IN, CE OUT is

actively pulled up to OUT.

The propagation delay through the chip-enable circuit-

ry depends on both the source impedance of the drive

to CE IN and the capacitive loading at CE OUT. The

chip-enable propagation delay is production tested

from the 50% point of CE IN to the 50% point of CE

OUT, using a 50Ω driver and 50pF load capacitance.

Minimize the capacitive load at CE OUT to minimize

propagation delay, and use a low-output-impedance

driver.

Backup-Battery Switchover

In a brownout or power failure, it may be necessary to

preserve the contents of the RAM. With a backup bat-

tery installed at BATT, the MAX6365–MAX6368 auto-

matically switch the RAM to backup power when VCC

falls. The MAX6367 has a BATT ON output that goes

high in battery-backup mode. These devices require

two conditions before switching to battery-backup

mode:

1) VCC must be below the reset threshold.

2) VCC must be below VBATT.

Table 1 lists the status of the inputs and outputs in bat-

tery-backup mode. The devices do not power up if the

only voltage source is on BATT. OUT only powers up

from VCC at startup.

Table 1. Input and Output Status in

Battery-Backup Mode

PIN

VCC

OUT

BATT

RESET/RESET

BATT ON

MR, RESET IN,

CE IN, WDI

CE OUT

STATUS

Disconnected from OUT

Connected to BATT

Connected to OUT. Current drawn from

the battery is less than 1µA (at VBATT =

2.8V, excluding IOUT) when VCC = 0.

Asserted

High state

Inputs ignored

Connected to OUT

Manual Reset Input (MAX6365 Only)

Many µP-based products require manual reset capabili-

ty, allowing the user or external logic circuitry to initiate a

reset. For the MAX6365, a logic low on MR asserts reset.

Reset remains asserted while MR is low and for a mini-

mum of 150ms (tRP) after it returns high. MR has an inter-

nal 20kΩ pullup resistor to VCC. This input can be driven

with TTL/CMOS logic levels or with open-drain/collector

outputs. Connect a normally open momentary switch

from MR to GND to create a manual reset function; exter-

nal debounce circuitry is not required. If MR is driven

from long cables or the device is used in a noisy environ-

ment, connect a 0.1µF capacitor from MR to GND to pro-

vide additional noise immunity.

VCC OR BATT

RESET

THRESHOLD VTH

CE IN

CE OUT

RESET-TO-CE OUT DELAY (12µs)

tRD

RESET

RESET

tRD

tRP

*

tRP

* IF CE IN GOES HIGH BEFORE RESET ASSERTS,

CE OUT GOES HIGH WITHOUT DELAY AS

CE IN GOES HIGH.

Figure 1. Reset and Chip-Enable Timing

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