M45PE10-VMN6TG View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

M45PE10-VMN6TG

1 Mbit, low voltage, Page-Erasable Serial Flash memory with byte-alterability and a 50 MHz SPI bus interface

STMicroelectronics 

Instructions

M45PE10

6.1

Write Enable (WREN)

The Write Enable (WREN) instruction (Figure 6) sets the Write Enable Latch (WEL) bit.

The Write Enable Latch (WEL) bit must be set prior to every Page Write (PW), Page

Program (PP), Page Erase (PE), and Sector Erase (SE) instruction.

The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the

instruction code, and then driving Chip Select (S) High.

Figure 6. Write Enable (WREN) instruction sequence

S

01234567

C

Instruction

D

High Impedance

Q

AI02281E

6.2

Write Disable (WRDI)

The Write Disable (WRDI) instruction (Figure 7) resets the Write Enable Latch (WEL) bit.

The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the

instruction code, and then driving Chip Select (S) High.

The Write Enable Latch (WEL) bit is reset under the following conditions:

● Power-up

● Write Disable (WRDI) instruction completion

● Page Write (PW) instruction completion

● Page Program (PP) instruction completion

● Page Erase (PE) instruction completion

● Sector Erase (SE) instruction completion

Figure 7. Write Disable (WRDI) instruction sequence

S

01234567

C

Instruction

D

High Impedance

Q

AI03750D

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