M30201F2TSP View Datasheet(PDF) - Mitsumi
Part Name
Description
MFG CO.
M30201F2TSP Datasheet PDF : 159 Pages
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CPU
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected
when this flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software
interrupt Nos. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight
processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt
is enabled.
• Bit 15: Reserved area
The C, Z, S, and O flags are changed when instructions are executed. See the software manual for
details.
b15
R0(Note)
H
b8 b7
b0
L
b15
R1(Note)
H
b8 b7
b0
L
b19
PC
b15
R2(Note)
Data
registers
b0
b19
INTB H
L
b15
b0
R3(Note)
b15
USP
b15
A0(Note)
b15
A1(Note)
b0
Address
b0
registers
b15
ISP
b15
SB
b15
FB(Note)
b0
Frame base
registers
b15
FLG
b0
Program coun
b0
Interrupt table
register
b0
User stack po
b0
Interrupt stack
pointer
b0
Static base
register
b0
Flag register
IPL
Figure 1.10. Flag register (FLG)
U I OB S Z D C
13
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