LTC6993MP View Datasheet(PDF) - Linear Technology

Part Name

Description

MFG CO.

LTC6993MP

TimerBlox: Monostable Pulse Generator (One Shot)

Linear Technology 

LTC6993-1/LTC6993-2

LTC6993-3/LTC6993-4

APPLICATIONS INFORMATION

ISET Extremes (Master Oscillator Frequency Extremes)

When operating with ISET outside of the recommended

1.25µA to 20µA range, the master oscillator operates

outside of the 62.5kHz to 1MHz range in which it is most

accurate.

The oscillator will still function with reduced accuracy for

ISET < 1.25µA. At approximately 500nA, the oscillator will

stop. Under this condition, the output pulse can still be

initiated, but will not terminate until ISET increases and

the master oscillator starts again.

At the other extreme, it is not recommended to operate

the master oscillator beyond 2MHz because the accuracy

of the DIV pin ADC will suffer.

Settling Time

Following a 2× or 0.5× step change in ISET , the output

pulse width takes approximately six master clock cycles

(6 • tMASTER) to settle to within 1% of the final value. An

example is shown in Figure 10, using the circuit in Figure 8.

VCTRL

2V/DIV

TRIG

5V/DIV

OUT

5V/DIV

PULSE WIDTH

2µs/DIV

LTC6993-1

V+ = 3.3V

DIVCODE = 0

RSET = 200k

RMOD = 464k

tOUT = 3µs AND 6µs

20µs/DIV

69931234 F10

Figure 10. Typical Settling Time

Coupling Error

The current sourced by the SET pin is used to bias the

internal master oscillator. The LTC6993 responds to

changes in ISET almost immediately, which provides excel-

lent settling time. However, this fast response also makes

the SET pin sensitive to coupling from digital signals, such

as the TRIG input.

Even an excellent layout will allow some coupling between

TRIG and SET. Additional error is included in the speci-

fied accuracy for NDIV = 1 to account for this. Figure 11

shows that ÷1 supply variation is dependent on coupling

from rising or falling trigger inputs and, to a lesser extent,

output polarity.

A very poor layout can actually degrade performance

further. The PCB layout should avoid routing SET next to

TRIG (or any other fast-edge, wide-swing signal).

1.0

0.8

0.6

LTC6993-1

0.4

POL = 1 LTC6993-1

0.2

POL = 0

0

–0.2

LTC6993-3

–0.4

POL = 0

–0.6

–0.8 RSET = 50k

NDIV = 1

–1.0

2

3

LTC6993-3

POL = 1

4

5

6

SUPPLY (V)

69931234 F11

Figure 11. tOUT Drift vs Supply Voltage

18

69931234fb

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