LTC3728LCGN(RevA) View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
LTC3728LCGN Datasheet PDF : 32 Pages
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LTC3728L/LTC3728LX
APPLICATIO S I FOR ATIO
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
IC. These items are also illustrated graphically in the
layout diagram of Figure 10. The Figure 11 illustrates the
current waveforms present in the various branches of the
2-phase synchronous regulators operating in the continu-
ous mode. Check the following in your layout:
1. Are the top N-channel MOSFETs M1 and M3 located
within 1cm of each other with a common drain connection
at CIN? Do not attempt to split the input decoupling for the
two channels as it can cause a large resonant loop.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return of
CINTVCC must return to the combined COUT (–) terminals.
The path formed by the top N-channel MOSFET, Schottky
diode and the CIN capacitor should have short leads and
PC trace lengths. The output capacitor (–) terminals
should be connected as close as possible to the (–)
terminals of the input capacitor by placing the capacitors
next to each other and away from the Schottky loop
described above.
3. Do the LTC3728L/LTC3728LX VOSENSE pins’ resistive
dividers connect to the (+) terminals of COUT? The resistive
divider must be connected between the (+) terminal of
R2
R1
RUN/SS1
SENSE1+
SENSE1–
VOSENSE1
PGOOD
TG1
SW1
BOOST1
PLLFLTR
fIN
VIN
PLLIN
BG1
INTVCC
FCB
EXTVCC
LTC3728L/LTC3728LX
ITH1
INTVCC
SGND
PGND
3.3V
3.3VOUT
BG2
ITH2
BOOST2
R3
R4
VOSENSE2
SENSE2–
SENSE2+
SW2
TG2
RUN/SS2
RPU
VPULL-UP
(<7V)
PGOOD
L1
RSENSE
CB1
M1
M2
D1
VOUT1
CINTVCC
CB2
RIN
CVIN
VIN
1µF
CERAMIC
CIN
1µF
CERAMIC
M3
M4
COUT1
COUT2
D2
RSENSE
L2
GND
VOUT2
3728 F10
26
Figure 10. LTC3728L/LTC3728LX Recommended Printed Circuit Layout Diagram
3728lxfa
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