LTC2234I View Datasheet(PDF) - Linear Technology

Part Name

Description

MFG CO.

LTC2234I

10-Bit, 135Msps ADC

Linear Technology 

LTC2234

10-Bit, 135Msps ADC

FEATURES

■ Sample Rate: 135Msps

■ 61dB SNR up to 200MHz Input

■ 75dB SFDR up to 400MHz Input

■ 775MHz Full Power Bandwidth S/H

■ Single 3.3V Supply

■ Low Power Dissipation: 630mW

■ CMOS Outputs

■ Selectable Input Ranges: ±0.5V or ±1V

■ No Missing Codes

■ Optional Clock Duty Cycle Stabilizer

■ Shutdown and Nap Modes

■ Data Ready Output Clock

■ Pin Compatible Family

135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit)

105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit)

80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit)

■ 48-Pin 7mm × 7mm QFN Package

U

APPLICATIO S

■ Wireless and Wired Broadband Communication

■ Cable Head-End Systems

■ Power Amplifier Linearization

■ Communications Test Equipment

DESCRIPTIO

The LTC®2234 is a 135Msps, sampling 10-bit A/D con-

verter designed for digitizing high frequency, wide dy-

namic range signals. The LTC2234 is perfect for demand-

ing communications applications with AC performance

that includes 60.5dB SNR and 75dB spurious free dy-

namic range for signals up to 400MHz. Ultralow jitter of

0.15psRMS allows undersampling of IF frequencies with

excellent noise performance.

DC specs include ±0.2LSB INL (typ), ±0.1LSB DNL (typ)

and ±0.8LSB INL, ±0.6LSB DNL over temperature. The

transition noise is a low 0.12LSBRMS.

A separate output power supply allows the CMOS output

swing to range from 0.5V to 3.6V.

The ENC+ and ENC– inputs may be driven differentially or

single ended with a sine wave, PECL, LVDS, TTL, or CMOS

inputs. An optional clock duty cycle stabilizer allows high

performance at full speed for a wide range of clock duty

cycles.

, LTC and LT are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

TYPICAL APPLICATIO

REFH

REFL

FLEXIBLE

REFERENCE

3.3V

VDD

ANALOG

INPUT

+

INPUT

S/H

–

10-BIT

PIPELINED

ADC CORE

CORRECTION

LOGIC

CLOCK/DUTY

CYCLE

CONTROL

ENCODE

INPUT

OUTPUT

DRIVERS

0.5V TO 3.6V

OVDD

D9

•

•

•

D0

OGND

2234 TA01

SFDR vs Input Frequency

90

85

4th OR HIGHER

80

75

2nd OR 3rd

70

65

60

55

50

0 100 200 300 400 500 600

INPUT FREQUENCY (MHz)

2234 TA01b

2234fa

1

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