APPLICATIONS INFORMATION
SCLK
VIL
t14
t15
DOUT
Figure 21. SCLK to DOUT Delay
VOH
VOL
1418 F21
LTC1418
24
CONVST
CONVST BUSY
RD
SCLK
LTC1418
CLKOUT
DOUT
EXT/INT
CS
25
26
BUSY (= RD)
23
17
18 CLKOUT ( = SCLK)
19
DOUT
20
μP OR DSP
(CONFIGURED
AS SLAVE)
OR
SHIFT
REGISTER
1418 F22a
(SAMPLE N)
CS = EXT/INT = 0
t5
CONVST
t6
(SAMPLE N + 1)
t13
t8
BUSY (= RD)
HOLD
SAMPLE
HOLD
CLKOUT (= SCLK)
t10
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
1
2
3
DOUT
Hi-Z D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DATA (N – 1)
tCONV
FILL
ZEROS
t7
Hi-Z
D13
D13 D12 D11
DATA N
t11
1418 F22b
CLKOUT
(= SCLK)
VIL
t14
t15
DOUT
D13
D12
VOH
D11
VOL
CAPTURE ON CAPTURE ON
RISING CLOCK FALLING CLOCK
Figure 22. Internal Conversion Clock Selected. Data Transferred During Conversion Using the ADC Clock Output as a Master
Shift Clock (SCLK Driven from CLKOUT)
For more information www.linear.com/LTC1418
1418fa
23