LTC1404(RevA) View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
LTC1404 Datasheet PDF : 24 Pages
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LTC1404
DIGITAL I PUTS AND OUTPUTS The ● denotes specifications which apply over the full operating temperature
range, unless otherwise noted specifications are at TA = 25°C. VCC = 5V, fSAMPLE = 600kHz, tr = tf = 5ns, unless otherwise specified.
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
IOZ
Hi-Z Output Leakage DOUT
VOUT = 0V to VCC
●
± 10
µA
COZ
Hi-Z Output Capacitance DOUT
15
pF
ISOURCE Output Source Current
VOUT = 0V
– 10
mA
ISINK
Output Sink Current
VOUT = VCC
10
mA
WU
TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range,
unless otherwise noted specifications are at TA = 25°C. VCC = 5V, fSAMPLE = 600kHz, tr = tf = 5ns, unless otherwise specified. See Figures
12, 13, 14.
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
fSAMPLE(MAX)
tCONV
tACQ
fCLK
tCLK
tWK(NAP)
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
Maximum Sampling Frequency
Conversion Time
Acquisition Time (Unipolar Mode)
(Bipolar Mode VSS = – 5V)
CLK Frequency
fCLK = 9.6MHz
CLK Pulse Width
(Notes 5 and 10)
Time to Wake Up from Nap Mode
CLK Pulse Width to Return to Active Mode
CONV↑ to CLK↑ Setup Time
CONV↑ After Leading CLK↑
CONV Pulse Width
(Note 9)
Time from CLK↑ to Sample Mode
Aperture Delay of Sample-and-Hold
Jitter < 50ps
Minimum Delay Between Conversion (Unipolar Mode)
(Note 5)
(Bipolar Mode VSS = – 5V)
Delay Time, CLK↑ to DOUT Valid
CLOAD = 20pF
Delay Time, CLK↑ to DOUT Hi-Z
CLOAD = 20pF
Time from Previous Data Remains Valid After CLK↑
CLOAD = 20pF
Minimum Time Between Nap/Sleep Request to Wake Up Request (Notes 5 and 10)
● 600
kHz
1.36
µs
200
ns
160
ns
● 0.1
9.6
MHz
● 40
ns
350
ns
● 40
ns
● 70
ns
●0
ns
● 40
ns
60
ns
40
ns
●
220 310
ns
●
180 300
ns
●
40
70
ns
●
40
70
ns
● 10
30
ns
● 50
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: When these pin voltages are taken below VSS (ground for unipolar
mode) or above VCC, they will be clamped by internal diodes. This product
can handle input currents greater than 60mA without latch-up if the pin is
driven below VSS (ground for unipolar mode) or above VCC.
Note 4: When these pin voltages are taken below VSS (ground for unipolar
mode), they will be clamped by internal diodes. This product can handle
input currents greater than 60mA without latch-up if the pin is driven
below VSS (ground for unipolar mode). These pins are not clamped to VCC.
Note 5: Guaranteed by design, not subject to test.
Note 6: Linearity, offset and full-scale specifications apply for unipolar and
bipolar modes.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 9: The rising edge of CONV starts a conversion. If CONV returns low
at a bit decision point during the conversion, it can create small errors. For
best performance, ensure that CONV returns low either within 100ns after
the conversion starts (i.e., before the first bit decision) or after the 14
clock cycles. (Figure 13 Timing Diagram).
Note 10: If this timing specification is not met, the device may not respond
to a request for a conversion. To recover from this condition a NAP
request is required.
1404fa
4
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