LTC1068 Series
ELECTRICAL CHARACTERISTICS LTC1068-25 (Internal Op Amps). The l denotes the specifications which
apply over the full operating temperature range, otherwise specifications are at VS = ± 5V, TA = 25°V, unless otherwise noted.
PARAMETER
Operating Supply Voltage Range
Voltage Swings
Output Short-Circuit Current (Source/Sink)
DC Open-Loop Gain
GBW Product
Slew Rate
Analog Ground Voltage (Note 4)
CONDITIONS
VS = 3.14V, RL = 5k (Note 2)
VS = 4.75V, RL = 5k (Note 3)
VS = ±5V, RL = 5k
VS = ± 4.75V
VS = ±5V
RL = 5k
VS = ±5V
VS = ±5V
VS = 5V, Voltage at AGND
MIN
TYP
MAX
3.14
± 5.5
l 1.2
1.6
l 2.6
3.4
l ±3.4
±4.1
17/6
20/15
85
6
10
2.5V ±2%
UNITS
V
VP-P
VP-P
V
mA
mA
dB
MHz
V/µs
V
LTC1068-25 (Complete Filter) VS = ± 5V, TA = 25°V, unless otherwise noted.
PARAMETER
CONDITIONS
Clock-to-Center Frequency Ratio (Note 5)
VS = 4.75V, fCLK = 500kHz, Mode 1 (Note 3),
fO = 20kHz, Q = 5, VIN = 0.5VRMS,
R1 = R3 = 49.9k, R2 = 10k
VS = ± 5V, fCLK = 1MHz, Mode 1,
fO = 40kHz, Q = 5, VIN = 1VRMS,
R1 = R3 = 49.9k, R2 = 10k
Clock-to-Center Frequency Ratio,
Side-to-Side Matching (Note 5)
Q Accuracy (Note 5)
fO Temperature Coefficient
Q Temperature Coefficient
VS = 4.75V, fCLK = 500kHz, Q = 5 (Note 3)
VS = ±5V, fCLK = 1MHz, Q = 5
VS = 4.75V, fCLK = 500kHz, Q = 5 (Note 3)
VS = ±5V, fCLK = 1MHz, Q = 5
DC Offset Voltage (Note 5)
(See Table 1)
VS = ± 5V, fCLK = 1MHz, VOS1
(DC Offset of Input Inverter)
VS = ± 5V, fCLK = 1MHz, VOS2
(DC Offset of First Integrator)
VS = ±5V, fCLK = 1MHz, VOS3
(DC Offset of Second Integrator)
Clock Feedthrough
Max Clock Frequency (Note 6)
Power Supply Current
VS = ± 5V, fCLK = 1MHz
VS = ±5V, Q ≤ 1.6, Mode 1
VS = 3.14V, fCLK = 1MHz (Note 2)
VS = 4.75V, fCLK = 1MHz (Note 3)
VS = ±5V, fCLK = 1MHz
MIN
l
l
l
l
l
l
l
l
l
l
l
l
TYP
25 ±0.3
25 ±0.3
± 0.25
± 0.25
±1
±1
±1
±5
0
–2
–5
0.25
5.6
3.5
6.5
9.5
MAX
25 ±0.8
25 ±0.9
UNITS
%
%
25 ±0.8
%
25 ±0.9
%
±0.9
%
±0.9
%
±3
%
±3
%
ppm/°C
ppm/°C
± 15
mV
±25
mV
±40
mV
mVRMS
MHz
8
mA
11
mA
15
mA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Production testing for single 3.14V supply is achieved by using
the equivalent dual supplies of ±1.57V.
Note 3: Production testing for single 4.75V supply is achieved by
using the equivalent dual supplies of ±2.375V.
Note 4: Pin 7 (AGND) is the internal analog ground of the device. For
single supply applications this pin should be bypassed with a 1µF
capacitor. The biasing voltage of AGND is set with an internal resistive
divider from Pin 8 to Pin 23 (see Block Diagram).
Note 5: Side D is guaranteed by design.
Note 6: See Typical Performance Characteristics.
1068fc
6