LTC1068-50CG View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
LTC1068-50CG Datasheet PDF : 30 Pages
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LTC1068 Series
PIN FUNCTIONS
Power Supply Pins
The V + and V– pins should each be bypassed with a
0.1µF capacitor to an adequate analog ground. The filter’s
power supplies should be isolated from other digital or
high voltage analog supplies. A low noise linear supply
is recommended. Using a switching power supply will
lower the signal-to-noise ratio of the filter. Figures 1 and 2
show typical connections for dual and single supply
operation.
Analog Ground Pin
The filter’s performance depends on the quality of the analog
signal ground. For either dual or single supply operation,
an analog ground plane surrounding the package is recom-
mended. The analog ground plane should be connected
to any digital ground at a single point. For single supply
operation, AGND should be bypassed to the analog ground
plane with at least a 0.47µF capacitor (Figure 2).
Two internal resistors bias the analog ground pin. For the
LTC1068, LTC1068-200 and LTC1068-25, the voltage at
the analog ground pin (AGND) for single supply is 0.5 × V+
and for the LTC1068-50 it is 0.435 × V+.
Clock Input Pin
Any TTL or CMOS clock source with a square-wave output
and 50% duty cycle (±10%) is an adequate clock source for
the device. The power supply for the clock source should
not be the filter’s power supply. The analog ground for the
filter should be connected to clock’s ground at a single
point only. Table 2 shows the clock’s low and high level
threshold values for dual or single supply operation.
Table 2. Clock Source High and Low Threshold Levels
POWER SUPPLY
HIGH LEVEL
LOW LEVEL
Dual Supply = ± 5V
≥ 1.53V
≤ 0.53V
Single Supply = 5V
≥ 1.53V
≤ 0.53V
Single Supply = 3.3V
≥ 1.20V
≤ 0.53V
A pulsed generator can be used as a clock source provided
the high level ON time is at least 25% of the pulse period.
Sine waves are not recommended for clock input frequen-
cies less than 100kHz, since excessively slow clock rise
or fall times generate internal clock jitter (maximum clock
rise or fall time ≤ 1µs). The clock signal should be routed
from the right side of the IC package and perpendicular to
it to avoid coupling to any input or output analog signal
ANALOG
GROUND
PLANE
V+
0.1µF
1
28
2
27
3
26
4
25
5
24
V–
0.1µF
6
23
7
22
LTC1068
8
21
9
20
10
19
11
18
12
17
13
16
14
15
ANALOG
1
28
GROUND
PLANE
2
27
DEVICE
RA RB
3
26
LTC1068
4
25
LTC1068-200 10k 10k
LTC1068-25
5
LTC1068-50 11.3k 8.6k 6
LTC1068
24
23
VAGND
V+
0.1µF
0.47µF
(1µF FOR
STOPBAND
FREQUENCIES
≤1kHz)
7
22
8 RA
RB
21
9
20
10
19
11
18
12
17
13
16
14
15
STAR
SYSTEM
GROUND
CLOCK
SOURCE
200Ω
DIGITAL GROUND
1068 F01
Figure 1. Dual Supply Ground Plane Connections
10
STAR
SYSTEM
GROUND
CLOCK
SOURCE
200Ω
FOR MODE 3, THE S NODE
SHOULD BE TIED TO PIN 7 (AGND)
DIGITAL GROUND
1068 F02
Figure 2. Single Supply Ground Plane Connections
1068fc
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