LM3S2110-IRN20-A2 View Datasheet(PDF) - Unspecified

Part Name

Description

MFG CO.

LM3S2110-IRN20-A2

Microcontroller

Unspecified 

Architectural Overview

• Output PWM signal is constructed based on actions taken as a result of the counter and

PWM comparator output signals

• Produces two independent PWM signals

– Dead-band generator

• Produces two PWM signals with programmable dead-band delays suitable for driving a

half-H bridge

• Can be bypassed, leaving input PWM signals unmodified

– Flexible output control block with PWM output enable of each PWM signal

• PWM output enable of each PWM signal

• Optional output inversion of each PWM signal (polarity control)

• Optional fault handling for each PWM signal

• Synchronization of timers in the PWM generator blocks

• Synchronization of timer/comparator updates across the PWM generator blocks

• Interrupt status summary of the PWM generator blocks

■ GPIOs

– 11-40 GPIOs, depending on configuration

– 5-V-tolerant input/outputs

– Programmable interrupt generation as either edge-triggered or level-sensitive

– Bit masking in both read and write operations through address lines

– Programmable control for GPIO pad configuration:

• Weak pull-up or pull-down resistors

• 2-mA, 4-mA, and 8-mA pad drive

• Slew rate control for the 8-mA drive

• Open drain enables

• Digital input enables

■ Power

– On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable

from 2.25 V to 2.75 V

– Low-power options on controller: Sleep and Deep-sleep modes

– Low-power options for peripherals: software controls shutdown of individual peripherals

24

November 29, 2007

Preliminary

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