LM3S2110-IRN20-A2 View Datasheet(PDF) - Unspecified

Part Name

Description

MFG CO.

LM3S2110-IRN20-A2

Microcontroller

Unspecified 

Architectural Overview

– 16-bit Input Capture modes

• Input edge count capture

• Input edge time capture

– 16-bit PWM mode

• Simple PWM mode with software-programmable output inversion of the PWM signal

■ ARM FiRM-compliant Watchdog Timer

– 32-bit down counter with a programmable load register

– Separate watchdog clock with an enable

– Programmable interrupt generation logic with interrupt masking

– Lock register protection from runaway software

– Reset generation logic with an enable/disable

– User-enabled stalling when the controller asserts the CPU Halt flag during debug

■ Controller Area Network (CAN)

– Supports CAN protocol version 2.0 part A/B

– Bit rates up to 1Mb/s

– 32 message objects, each with its own identifier mask

– Maskable interrupt

– Disable automatic retransmission mode for TTCAN

– Programmable loop-back mode for self-test operation

■ Synchronous Serial Interface (SSI)

– Master or slave operation

– Programmable clock bit rate and prescale

– Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep

– Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments

synchronous serial interfaces

– Programmable data frame size from 4 to 16 bits

– Internal loopback test mode for diagnostic/debug testing

■ UART

– Fully programmable 16C550-type UART with IrDA support

22

November 29, 2007

Preliminary

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