LM3S2110-IRN20-A2 View Datasheet(PDF) - Unspecified

Part Name

Description

MFG CO.

LM3S2110-IRN20-A2

Microcontroller

Unspecified 

LM3S2110 Microcontroller

– Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt

handling

– 26 interrupts with eight priority levels

– Memory protection unit (MPU), providing a privileged mode for protected operating system

functionality

– Unaligned data access, enabling data to be efficiently packed into memory

– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined

peripheral control

■ Internal Memory

– 64 KB single-cycle flash

• User-managed flash block protection on a 2-KB block basis

• User-managed flash data programming

• User-defined and managed flash-protection block

– 16 KB single-cycle SRAM

■ General-Purpose Timers

– Three General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers.

Each GPTM can be configured to operate independently:

• As a single 32-bit timer

• As one 32-bit Real-Time Clock (RTC) to event capture

• For Pulse Width Modulation (PWM)

– 32-bit Timer modes

• Programmable one-shot timer

• Programmable periodic timer

• Real-Time Clock when using an external 32.768-KHz clock as the input

• User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU

Halt flag during debug

– 16-bit Timer modes

• General-purpose timer function with an 8-bit prescaler

• Programmable one-shot timer

• Programmable periodic timer

• User-enabled stalling when the controller asserts CPU Halt flag during debug

November 29, 2007

21

Preliminary

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