LH540203
TIMING DIAGRAMS (cont’d)
CMOS 2048 × 9 Asynchronous FIFO
LAST WRITE
R
W
t WFF
FF
FIRST READ
tRFF
Figure 12. Full Flag From Last Write to First Read
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LAST READ
W
FIRST WRITE
R
t REF
t WEF
EF
NOTE: The Data Out pins (D0 - D8) are forced into a
high-impedance state whenever EF = LOW.
Figure 13. Empty Flag From Last Read to First Write
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12