Philips Semiconductors
Multimedia video data acquisition circuit
Objective specification
SAA5284
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
I2C-bus timings (see note 2 and Fig.8)
fi(SCL)
tLOW
tHIGH
tSU;DAT
tHD;DAT
tSU;STO
tBUF
tHD;STA
tSU;STA
tr
tf
SCL input clock frequency
SCL LOW time
SCL HIGH time
data set-up time
data hold time
set-up time STOP condition
bus free time
hold time START condition
set-up time repeated START
rise time (SDA and SCL)
fall time (SDA and SCL)
fi(SCL) = 100 kHz
fi(SCL) = 400 kHz
fi(SCL) = 100 kHz
fi(SCL) = 400 kHz
fi(SCL) = 100 kHz
fi(SCL) = 400 kHz
fi(SCL) = 100 kHz
fi(SCL) = 400 kHz
fi(SCL) = 100 kHz
fi(SCL) = 400 kHz
fi(SCL) = 100 kHz
fi(SCL) = 400 kHz
fi(SCL) = 100 kHz
fi(SCL) = 400 kHz
fi(SCL) = 100 kHz
fi(SCL) = 400 kHz
fi(SCL) = 100 kHz
fi(SCL) = 400 kHz
fi(SCL) = 100 kHz
fi(SCL) = 400 kHz
fi(SCL) = 100 kHz
fi(SCL) = 400 kHz
0
−
0
−
4.7
−
1.3
−
4.0
−
0.6
−
250 −
100 −
0
−
0
−
4.7
−
0.6
−
4.7
−
1.3
−
4.0
−
0.6
−
4.7
−
0.6
−
−
−
−
−
−
−
−
−
100
kHz
400
kHz
−
µs
−
µs
−
µs
−
µs
−
ns
−
ns
−
µs
−
µs
−
µs
−
µs
−
µs
−
µs
−
µs
−
µs
−
µs
−
µs
1 000
ns
300
ns
300
ns
300
ns
Notes
1. ESD protection of this pin falls below the Philips General Quality Specification (GQS). Therefore it is recommended
that a diode is connected from pin RDY to VDDD.
2. The I2C-bus interface pins SDA and SCL may pull the data and clock lines below 3 V while the digital power supply
VDDD is in the range 0.4 to 0.8 V.
1998 Feb 05
11