74F1604 View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
74F1604 Datasheet PDF : 10 Pages
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Philips Semiconductors
Latch
Product specification
74F1604
FEATURES
• High impedance NPN base inputs for reduced loading
(20µA in high and low state)
• Stores 16–bit wide data inputs, multiplexed 8–bit outputs
• Propagation delay 7.0ns typical
• Power supply current 70mA typical
DESCRIPTION
The 74F1604 is a dual octal transparent latch. Organized as 8–bit A
and B latches, the latch outputs are connected by pairs to eight
2–input multiplexers. A select (SELECT A/B) input determines
whether the A or B latch contents are multiplexed to the eight
outputs. Data from the B inputs are selected when SELECT A/B is
low; data from the A inputs are selected when SELECT A/B is high.
Data enters the latch on the falling edge of the latch enable (LE)
input. The latch remains transparent to the data inputs while LE is
low, and stores the data that is present one setup time before the
low–to–high latch enable transition.
TYPE
74F1604
TYPICAL
PROPAGATION DELAY
7.0ns
TYPICAL SUPPLY
CURRENT (TOTAL)
70mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION COMMERCIAL RANGE
28–pin plastic DIP
28–pin plastic SOL
VCC = 5V ±10%,
Tamb = 0°C to +70°C
N74F1604N
N74F1604D
PKG DWG #
SOT117-2
SOT136-1
INPUT AND OUTPUT LOADING
AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.) LOAD VALUE
HIGH/LOW HIGH/LOW
A0 – A7 Data inputs
1.0/0.033
20µA/20µA
B0 – B7 Data inputs
1.0/0.033
20µA/20µA
SELECT
A/B
Select input
1.0/0.033
20µA/20µA
LE
Latch enable input
(active low)
1.0/0.033
20µA/20µA
Q0 – Q7 Data outputs
50/33
1.0mA/20mA
Note to input and output loading and fan out table
One (1.0) FAST unit load is defined as: 20µA in the high state and
0.6mA in the low state.
PIN CONFIGURATION
LE 1
SELECT A/B 2
A0 3
B0 4
A1 5
B1 6
A2 7
B2 8
A3 9
B3 10
Q3 11
Q2 12
Q1 13
GND 14
28 VCC
27 A4
26 B4
25 A5
24 B5
23 A6
22 B6
21 A7
20 B7
19 Q7
18 Q6
17 Q5
16 Q4
15 Q
SF00553
LOGIC SYMBOL
3 4 5 6 7 8 9 10 27 26 25 24 2322 21 20
A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6B6A7 B7
1
LE
2
SELCT A/B
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
VCC = Pin 28
GND = Pin 14
15 13 12 11 16 17 18 19
SF00554
IEC/IEEE SYMBOL
2
G2
1
C1
3
1D 2
4
1D 2
5
6
7
8
9
10
27
26
25
24
23
22
21
20
1
15
13
12
11
16
17
18
19
SF00555
October 4, 1990
2
853 0088 00619
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