MC10H166
A4 9
B4 10
LOGIC DIAGRAM
A3 12
B3 11
2A>B
A2 13
B2 14
A1 6
B1 7
A0 5
B0 4
E 15
3A<B
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
FIGURE 1 — 9–BIT MAGNITUDE COMPARA-
TOR
A0 B0 A1 B1 A2 B2 A3 B3 A4 B4
A5 B5 A6 B6 A7 B7 A8 B8
A0 A1 A2 A3 A4
B0 B1 B2 B3 B4
MC10H166
A>B
A<B
A0 A1 A2 A3 A4
B0 B1 B2 B3 B4
A>B
A<B
A>B A<B A = B
For 9–Bit Word
For longer word lengths, the MC10H166 can be serially
expanded or cascaded. Figure 1 shows two devices in a
serial expansion for a 9–bit word length. The A > B and
A < B outputs are fed to the A0 and B0 inputs respectively
of the next device. The connection for an A = B output is
also shown. The worst case delay time of serial
expansion is equal to the number of comparators times
the data–to–output delay.
MECL Data
DL122 — Rev 6
2–267
MOTOROLA