ISL95870BHRZ-T View Datasheet(PDF) - Intersil
Part Name
Description
MFG CO.
ISL95870BHRZ-T Datasheet PDF : 29 Pages
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ISL95870, ISL95870A, ISL95870B
Figure 17 shows the overcurrent set circuit. The inductor
consists of inductance L and the DC resistance DCR. The
inductor DC current IL creates a voltage drop across
DCR, which is given by Equation 31:
VDCR = IL ⋅ DCR
(EQ. 31)
The IOCSET current source sinks 8.5µA into the OCSET
pin, creating a DC voltage drop across the resistor
ROCSET, which is given by Equation 32:
VROCSET = 8.5μA ⋅ ROCSET
(EQ. 32)
The DC voltage difference between the OCSET pin and
the VO pin, which is given by Equation 33:
VOCSET– VVO = VDCR– VROCSET =IL ⋅DCR – IOCSET⋅ ROCSET
(EQ. 33)
The IC monitors the voltage of the OCSET pin and the VO
pin. When the voltage of the OCSET pin is higher than
the voltage of the VO pin for more than 10µs, an OCP
fault latches the converter off.
The value of ROCSET is calculated with Equation 34,
which is written as:
ROCSET
=
I--O-----C-----⋅---D-----C-----R--
IOCSET
(EQ. 34)
Where:
- ROCSET (Ω) is the resistor used to program the
overcurrent setpoint
- IOC is the output DC load current that will activate
the OCP fault detection circuit
- DCR is the inductor DC resistance
For example, if IOC is 20A and DCR is 4.5mΩ, the choice
of ROCSET is equal to 20A x 4.5mΩ/8.5µA = 10.5kΩ.
Resistor ROCSET and capacitor CSEN form an R-C
network to sense the inductor current. To sense the
inductor current correctly not only in DC operation, but
also during dynamic operation, the R-C network time
constant ROCSET CSEN needs to match the inductor time
constant L/DCR. The value of CSEN is then written as
Equation 35:
CSEN = -R----O-----C----S----E--L--T----⋅---D-----C-----R---
(EQ. 35)
For example, if L is 1.5µH, DCR is 4.5mΩ, and ROCSET is
9kΩ, the choice of CSEN = 1.5µH/(9kΩ x 4.5mΩ) = 0.037µF.
When an OCP fault is declared, the converter will be
latched off and the PGOOD pin will be asserted low. The
fault will remain latched until the EN pin has been pulled
below the falling EN threshold voltage VENTHF or if VCC
has decayed below the falling POR threshold voltage
VVCC_THF.
Overvoltage
The OVP fault detection circuit triggers after the FB pin
voltage is above the rising overvoltage threshold VOVRTH
for more than 2µs. For example, if the converter is
programmed to regulate 1.0V at the FB pin, that voltage
would have to rise above the typical VOVRTH threshold of
116% for more than 2µs in order to trip the OVP fault
latch. In numerical terms, that would be
116% x 1.0V = 1.16V. When an OVP fault is declared,
the converter will be latched off and the PGOOD pin will
be asserted low. The fault will remain latched until the EN
pin has been pulled below the falling EN threshold
voltage VENTHF or if VCC has decayed below the falling
POR threshold voltage VVCC_THF.
Although the converter has latched-off in response to an
OVP fault, the LGATE gate-driver output will retain the
ability to toggle the low-side MOSFET on and off, in
response to the output voltage transversing the VOVRTH
and VOVFTH thresholds. The LGATE gate-driver will turn-
on the low-side MOSFET to discharge the output voltage,
protecting the load. The LGATE gate-driver will turn-off
the low-side MOSFET once the FB pin voltage is lower
than the falling overvoltage threshold VOVRTH for more
than 2µs. The falling overvoltage threshold VOVFTH is
typically 102%. That means if the FB pin voltage falls
below 102% x 1.0V = 1.02V for more than 2µs, the
LGATE gate-driver will turn off the low-side MOSFET. If
the output voltage rises again, the LGATE driver will
again turn on the low-side MOSFET when the FB pin
voltage is above the rising overvoltage threshold
VOVRTH for more than 2µs. By doing so, the IC protects
the load when there is a consistent overvoltage
condition.
Undervoltage
The UVP fault detection circuit triggers after the FB pin
voltage is below the undervoltage threshold VUVTH for
more than 2µs. For example if the converter is
programmed to regulate 1.0V at the FB pin, that voltage
would have to fall below the typical VUVTH threshold of
84% for more than 2µs in order to trip the UVP fault
latch. In numerical terms, that would be
84% x 1.0V = 0.84V. When a UVP fault is declared, the
converter will be latched off and the PGOOD pin will be
asserted low. The fault will remain latched until the EN
pin has been pulled below the falling EN threshold
vPoOlRtatghereVsEhNoTlHdFvoorltaifgVeCVCVChCas_TdHeFc.ayed below the falling
Over-Temperature
When the temperature of the IC increases above the
rising threshold temperature TOTRTH, it will enter the OTP
state that suspends the PWM, forcing the LGATE and
UGATE gate-driver outputs low. The status of the PGOOD
pin does not change nor does the converter latch-off. The
PWM remains suspended until the IC temperature falls
below the hysteresis temperature TOTHYS at which time
normal PWM operation resumes. The OTP state can be
reset if the EN pin is pulled below the falling EN threshold
voltage VENTHF or if VCC has decayed below the falling
POR threshold voltage VVCC_THF. All other protection
circuits remain functional while the IC is in the OTP state.
It is likely that the IC will detect an UVP fault because in
the absence of PWM, the output voltage decays below
the undervoltage threshold VUVTH.
21
FN6899.0
December 22, 2009
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