ISL85402EVAL1Z View Datasheet(PDF) - Intersil

Part Name

Description

MFG CO.

ISL85402EVAL1Z

2.5A Regulator with Integrated High-Side MOSFET for Synchronous Buck or Boost Buck Converter

Intersil 

ISL85402

1200

1000

800

600

400

200

0

0

500

1000

1500

FS (kHz)

FIGURE 27. RFS vs FREQUENCY

2000

2500

The SYNC pin is bi-directional and it outputs the IC’s default or

programmed local clock signal when it’s free running. The IC

locks to an external clock injected to the SYNC pin (external clock

frequency recommended to be 10% higher than the free running

frequency). The delay from the rising edge of the external clock

signal to the PHASE rising edge is half of the free running switching

period pulse 220ns, (0.5Tsw+220ns). The maximum external clock

frequency is recommended to be 1.6 of the free running frequency.

When the part enters PFM pulse skipping mode, the

synchronization function is shut off and also no clock signal

output in SYNC pin.

With the SYNC pins simply connected together, multiple

ISL85402s can be synchronized. The slave ICs automatically

have 180° phase shift with respective to the master IC.

Fault Protection

Overcurrent Protection

The overcurrent function protects against any overload condition

and output short at worst case, by monitoring the current flowing

through the upper MOSFET.

There are 2 current limiting thresholds. The first one IOC1 is to

limit the high-side MOSFET peak current cycle-by-cycle. The

current limit threshold is set to default at 3.6A with ILIMIT pin

connected to GND or VCC, or left open. The current limit threshold

can also be programmed by a resistor RLIM at ILIMIT pin to

ground. Use Equation 10 to calculate the resistor.

RLIM

=

-------------3-----0-----0-----0-----0-----0---------------

IOC[A] + 0.018

(EQ. 10)

Note that IOC1 is higher with lower RLIM. Considering the OC

programming circuit tolerances over the temperature range -

40°C to 105°C, 71.5k is the lowest resistor value recommended

to be used for RLIM to achieve the highest OC threshold. With

71.5k RLIM, the OC limit is 4.18A (TYP). A resistor lower than

71.5k would result in a default 3.6A OC1 threshold.

The second current protection threshold IOC2 is 15% higher than

IOC1 mentioned previously. Instantly after the high-side MOSFET

current reaches IOC2, the PWM is shut off after 2-cycle delay and the

IC enters hiccup mode. In hiccup mode, the PWM is disabled for

dummy soft-start duration equaling to 5 regular soft-start periods.

After this dummy soft-start cycle, the true soft-start cycle is

attempted again. The IOC2 offers a robust and reliable protections

against the worst case conditions.

The frequency foldback is implemented for the ISL85402. When

overcurrent limiting, the switching frequency is reduced to be

proportional to output voltage in order to keep the inductor

current under limit threshold during overload condition. The low

limit of frequency under frequency foldback operation is 40kHz.

370

320

270

220

170

120

70

0.0

1.0

2.0

3.0

4.0

5.0

6.0

IOC1 (A)

FIGURE 28. RLIM vs IOC1

Overvoltage Protection

If the voltage detected on the FB pin is over 110% of reference,

the high-side and low-side driver shuts down immediately and

won’t be allowed on until FB voltage drops to 0.8V. When the FB

voltage drops to 0.8V, the drivers are released to ON. If the 120%

overvoltage threshold is reached, the high-side and low-side

driver shuts down immediately and the IC is latched off. The IC

has to be reset for restart.

Thermal Protection

The ISL85402 PWM will be disabled if the junction temperature

reaches +155°C. A +15°C hysteresis insures that the device will

not restart until the junction temperature drops below +140°C.

Component Selections

The ISL85402 iSim model, which is available on the internet can

be used to simulate the behaviors to, which will assist with the

design.

Output Capacitors

An output capacitor is required to filter the inductor current.

Output ripple voltage and transient response are 2 critical factors

when considering output capacitance choice. The current mode

control loop allows for the usage of low ESR ceramic capacitors

and thus smaller board layout. Electrolytic and polymer

capacitors may also be used.

Additional consideration applies to ceramic capacitors. While

they offer excellent overall performance and reliability, the actual

in-circuit capacitance must be considered. Ceramic capacitors

are rated using large peak-to-peak voltage swings with no DC

bias. In the DC/DC converter application, these conditions do not

16

FN7640.1

April 25, 2013

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