FB2041 View Datasheet(PDF) - Philips Electronics

Part Name

Description

MFG CO.

FB2041

7-bit Futurebus+ transceiver

Philips Electronics 

Philips Semiconductors

7-bit Futurebus+ transceiver

PIN CONFIGURATION

52 51 50 49 48 47 46 45 44 43 42 41 40

LOGIC GND 1

AI1 2

AI2 3

AO2 4

LOGIC GND 5

AO3 6

LOGIC GND 7

AI3 8

AI4 9

AO4 10

LOGIC GND 11

AO5 12

LOGIC GND 13

7-Bit Transceiver

FB2041

52-lead PQFP

39 BUS GND

38 B1

37 BUS GND

36 B2

35 BUS GND

34 B3

33 BUS GND

32 B4

31 BUS GND

30 B5

29 BUS GND

28 B6

27 BUS GND

14 15 16 17 18 19 20 21 22 23 24 25 26

Product specification

FB2041

The B-port interfaces to “Backplane Transceiver Logic” (See the

IEEE 1194.1 BTL standard). BTL features low power consumption

by reducing voltage swing (1Vp-p, between 1V and 2V) and reduced

capacitive loading by placing an internal series diode on the drivers.

BTL also provides incident wave switching, a necessity for high

performance backplanes.

There are three separate pairs of driver enables in a 1 bit, 3 bit, 3 bit

arrangement. The TTL/BTL output drivers for bit 0 are enabled with

OEA1/OEB1, output drivers for bits 1–2–3 are enabled with

OEA2/OEB2 and output drivers for bits 4–5–6 are enabled with

OEA3/OEB3.

The A-port operates at TTL levels with separate I/O. The 3-state

A-port drivers are enabled when OEAn goes High after an extra 6ns

delay which is built in to provide a break-before-make function.

When OEAn goes Low, A-port drivers become High impedance

without any extra delay. During power on/off cycles, the A-port

drivers are held in a High impedance state when VCC is below 2.5V.

The B-port has an output enable, OEB0, which affects all seven

drivers. When OEB0 is High and OEBn is Low the output driver will

be enabled. When OEB0 is Low or if OEBn is High, the B-port

drivers will be inactive and at the level of the backplane signal.

To support live insertion, OEB0 is held Low during power on/off

cycles to insure glitch free B port drivers. Proper bias for B port

drivers during live insertion is provided by the BIAS V pin when at a

5V level while VCC is Low. If live insertion is not a requirement, the

BIAS V pin should be tied to a VCC pin.

The LOGIC GND and BUS GND pins are isolated in the package to

minimize noise coupling between the BTL and TTL sides. These

pins should be tied to a common ground external to the package.

Each BTL driver has an associated BUS GND pin that acts as a

signal return path and these BUS GND pins are internally isolated

from each other. In the event of a ground return fault, a “hard” signal

failure occurs instead of a pattern dependent error that may be very

infrequent and impossible to trouble-shoot.

The LOGIC VCC and BUS VCC pins are also isolated internally to

minimize noise and may be externally decoupled separately or

simply tied together.

JTAG boundary scan functionality is provided as an option with

signals TMS, TCK, TDI and TDO. When this option is not present,

TMS and TCK are no-connects (no bond wires) and TDI and TDO

are shorted together internally.

1995 May 25

3

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