IDT82V3385(2009) View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

MFG CO.

IDT82V3385
(Rev.:2009)

SYNCHRONOUS ETHERNET WAN PLL

Integrated Device Technology 

IDT82V3385

SYNCHRONOUS ETHERNET WAN PLL

Table 1: Pin Description (Continued)

Name

IN4_POS

IN4_NEG

IN5

FRSYNC_8K

MFRSYNC_2K

OUT1

OUT2

OUT3

OUT4_POS

OUT4_NEG

OUT5_POS

OUT5_NEG

CS

INT_REQ

Pin No.

42

43

54

30

31

90

93

94

34

35

36

37

70

8

I/O

Type

Description 1

IN4_POS / IN4_NEG: Positive / Negative Input Clock 4

A N x 2 kHz, N x 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz,

I

PECL/LVDS 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 156.25 MHz,

311.04 MHz or 622.08 MHz clock is differentially input on this pair of pins. Whether the clock

signal is PECL or LVDS is automatically detected.

I

pull-down

CMOS

IN5: Input Clock 5

A N x 2 kHz, N x 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz,

19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on

this pin.

In Slave operation, the frequency of the T0 selected input clock IN5 is recommended to be

6.48 MHz.

Output Frame Synchronization Signal

O

CMOS

FRSYNC_8K: 8 kHz Frame Sync Output

An 8 kHz signal is output on this pin.

O

CMOS

MFRSYNC_2K: 2 kHz Multiframe Sync Output

A 2 kHz signal is output on this pin.

Output Clock

OUT1: Output Clock 1

A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7,

O

CMOS 5 MHz, 10 MHz, 20 MHz, 25 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz,

51.84 MHz, 77.76 MHz, 125 MHz, 155.52 MHz, 156.25 MHz or 312.5 MHz clock is output on

this pin.

OUT2: Output Clock 2

O

CMOS A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7,

5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,

77.76 MHz or 155.52 MHz clock is output on this pin.

OUT3: Output Clock 3

O

CMOS A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7,

5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,

77.76 MHz or 155.52 MHz clock is output on this pin.

OUT4_POS / OUT4_NEG: Positive / Negative Output Clock 4

A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7,

O PECL/LVDS 5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,

77.76 MHz, 155.52 MHz, 311.04 MHz or 622.08 MHz clock is differentially output on this pair

of pins.

OUT5_POS / OUT5_NEG: Positive / Negative Output Clock 5

A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7,

O PECL/LVDS 5 MHz, 10 MHz, 20 MHz, 25 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz,

51.84 MHz, 77.76 MHz, 125 MHz, 155.52 MHz, 311.04 MHz, 312.5 MHz or 622.08 MHz

clock is differentially output on this pair of pins.

Microprocessor Interface

I

pull-up

O

CMOS

CMOS

CS: Chip Selection

A transition from high to low must occur on this pin for each read or write operation and this

pin should remain low until the operation is over.

INT_REQ: Interrupt Request

This pin is used as an interrupt request. The output characteristics are determined by the

HZ_EN bit (b1, 0CH) and the INT_POL bit (b0, 0CH).

Pin Description

14

March 23, 2009

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