IDT82V3002A WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE RANGE
Table - 1 Pin Description (Continued)
Name
Type
Pin
Number
Description
TCK
I
28
Test Clock.
Provides a clock to JTAG test logic.
TMS
I
31
Test Mode Select.
JTAG signal that controls the state transitions of the TAP controller. This pin is internally pulled up to VDD.
IC0, IC1, IC2
-
53, 54, 55
Internal Connection.
Internal Use. These pins should be connected to VSS when in normal operation.
IC
-
8, 21, 22, Internal Connection.
34, 35, 43 Internal Use. These pins should be left open when in normal operation.
9