72T7285 View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

MFG CO.

72T7285

(IDT72T72xxx) 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 72-BIT CONFIGURATIONS

Integrated Device Technology 

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ 72-BIT FIFO

16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72

PARTIAL RESET (PRS) MASTER RESET (MRS)

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

WRITE CLOCK (WCLK/WR)

WRITE ENABLE (WEN)

WRITE CHIP SELECT (WCS)

LOAD (LD)

(x72, x36, x18) DATA IN (D0 - Dn)

SERIAL CLOCK (SCLK)

SERIAL ENABLE(SEN)

FIRST WORD FALL THROUGH/

SERIAL INPUT (FWFT/SI)

FULL FLAG/INPUT READY (FF/IR)

PROGRAMMABLE ALMOST-FULL (PAF)

IDT

72T7285

72T7295

72T72105

72T72115

READ CLOCK (RCLK/RD)

READ ENABLE (REN)

OUTPUT ENABLE (OE)

READ CHIP SELECT (RCS)

(x72, x36, x18) DATA OUT (Q0 - Qn)

RCLK ECHO, ERCLK

REN ECHO, EREN

MARK

RETRANSMIT (RT)

EMPTY FLAG/OUTPUT READY (EF/OR)

PROGRAMMABLE ALMOST-EMPTY (PAE)

HALF-FULL FLAG (HF)

BIG-ENDIAN/LITTLE-ENDIAN (BE)

INTERSPERSED/

NON-INTERSPERSED PARITY (IP)

INPUT WIDTH (IW) BUS- OUTPUT WIDTH (OW)

MATCHING

(BM)

5994 drw03

Figure 1. Single Device Configuration Signal Flow Diagram

TABLE 1 — BUS-MATCHING CONFIGURATION MODES

BM

IW

OW

Write Port Width

L

L

L

x72

H

L

L

x72

H

L

H

x72

H

H

L

x36

H

H

H

x18

NOTE:

1. Pin status during Master Reset.

Read Port Width

x72

x36

x18

x72

x72

5

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