IDT723676L12PF View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
MFG CO.
IDT723676L12PF
Integrated Device Technology
IDT723676L12PF Datasheet PDF : 39 Pages
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IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
Data is read from FIFO1 to the B0-B17 outputs by a LOW-to-HIGH
transition of CLKB when CSB is LOW, RENB is HIGH, MBB is LOW and EFB/
ORB is HIGH (see Table 3). FIFO reads on Port B are independent of any
concurrent Port A and Port C operations.
Data is loaded into FIFO2 from the C0-C17 inputs on a LOW-to-HIGH
transition of CLKC when WENB is HIGH, MBC is LOW, and FFC/IRC is HIGH
(see Table 4). FIFO writes on Port C are independent of any concurrent Port
A and Port B operation.
The setup and hold time constraints for CSA and W/RA with regard to CLKA
as well as CSB with regard to CLKB are only for enabling write and read
operations and are not related to high-impedance control of the data outputs.
If ENA is LOW during a clock cycle, either CSA or W/RA may change states
during the setup and hold time window of the cycle. This is also true for CSB
when RENB is LOW.
When operating the FIFO in FWFT mode and the Output Ready flag is LOW,
the next word written is automatically sent to the FIFO’s output register by the
LOW-to-HIGH transition of the port clock that sets the Output Ready flag HIGH.
When the Output Ready flag is HIGH, subsequent data is clocked to the output
registers only when a read is selected using CSA, W/RA, ENA and MBA at Port
A or using CSB, RENB and MBB at Port B.
When operating the FIFO in IDT Standard mode, the first word will cause the
Empty Flag to change state on the second LOW-to-HIGH transition of the Read
Clock. The data word will not be automatically sent to the output register. Instead,
data residing in the FIFO’s memory array is clocked to the output register only
when a read is selected using CSA, W/RA, ENA and MBA at Port A or using
CSB, RENB and MBB at Port B. Relevant write and read timing diagrams for
Port A can be found in Figure 10 and 15. Relevant read and write timing
diagrams for Port B and Port C, together with Bus-Matching and Endian select
operation, can be found in Figure 11 to 14.
LOOPBACK (LOOP)
A Loopback function is provided on Port A and is selected by setting the LOOP
pin LOW. When the Loop feature is selected, the data output from FIFO2 will be
directed to the data input of FIFO1. If Loop is selected and Port A is set-up for
write operation via the W/RA pin being HIGH, then data output from FIFO2 will
be written to FIFO1, on every LOW-to-HIGH transition of CLKA, provided CSA
is LOW and ENA is HIGH. However, FIFO2 data output will not be placed on
the output Port A (A0-A35). If Port A is set-up for read operation via the W/RA
pin being LOW, then data output from FIFO2 will be written into FIFO1 on every
LOW-to-HIGH transition of CLKA, provided CSA is LOW and ENA is HIGH. Also
FIFO2 data will be output to Port A (A0-A35). When the LOOP pin is HIGH then
Port A operates in the normal manner. Refer to Table 2 for the input set-up of
the Loop feature.
The Loop operation will continue to happen provided that FIFO1 is not full
and FIFO2 is not empty. If during a Loop sequence FIFO1 becomes full then
any data that continues to be read out from FIFO2 will only be placed on the
TABLE 5 — FIFO1 FLAG OPERATION (IDT Standard and FWFT modes)
Number of Words in FIFO Memory(1,2)
Synchronized
to CLKB
Synchronized
to CLKA
IDT723656(3)
IDT723666(3)
IDT723676(3)
EFB/ORB
AEB
AFA
FFA/IRA
0
0
0
L
L
H
H
1 to X1
1 to X1
1 to X1
H
L
H
H
(X1+1) to [2,048-(Y1+1)]
(X1+1) to [4,096-(Y1+1)]
(X1+1) to [8,192-(Y1+1)]
H
H
H
H
(2,048-Y1) to 2,047
(4,096-Y1) to 4,095
(8,192-Y1) to 8,191
H
H
L
H
2,048
4,096
8,192
H
H
L
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no read operation
necessary), it is not included in the FIFO memory count.
3. X1 is the almost-empty offset for FIFO1 used by AEB. Y1 is the almost-full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset or port A programming.
4. The ORB and IRA functions are active during FWFT mode; the EFB and FFA functions are active in IDT Standard mode.
TABLE 6 — FIFO2 FLAG OPERATION (IDT Standard and FWFT modes)
Number of Words in FIFO Memory(1,2)
Synchronized
to CLKA
Synchronized
to CLKC
IDT723656(3)
IDT723666(3)
IDT723676(3)
EFA/ORA
AEA
AFC
FFC/IRC
0
0
0
L
L
1 to X2
1 to X2
1 to X2
H
L
(X2+1) to [2,048-(Y2+1)]
(X2+1) to [4,096-(Y2+1)]
(X2+1) to [8,192-(Y2+1)]
H
H
H
H
H
H
H
H
(2,048-Y2) to 2,047
(4,096-Y2) to 4,095
(8,192-Y2) to 8,191
H
H
L
H
2,048
4,096
8,192
H
H
L
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no read operation
necessary), it is not included in the FIFO memory count.
3. X2 is the almost-empty offset for FIFO2 used by AEA. Y2 is the almost-full offset for FIFO2 used by AFC. Both X2 and Y2 are selected during a FIFO2 reset or port A programming.
4. The ORA and IRC functions are active during FWFT mode; the EFA and FFC functions are active in IDT Standard mode.
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