Product Type
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
Organization
Label Code
Jedec SPD Revision
Byte# Description
29
tRCD.min [ns]
30
tRAS.min [ns]
31 Module Density per Rank
32
tAS.min and tCS.min [ns]
33
tAH.min and tCH.min [ns]
34
tDS.min [ns]
35
tDH.min [ns]
36
tWR.min [ns]
37
tWTR.min [ns]
38
tRTP.min [ns]
39 Analysis Characteristics
40
tRC and tRFC Extension
41
tRC.min [ns]
42
tRFC.min [ns]
43
tCK.max [ns]
44
tDQSQ.max [ns]
45
tQHS.max [ns]
46 PLL Relock Time
47
TCASE.max Delta / ∆ T4R4W Delta
48 Psi(T-A) DRAM
49
∆ T0
50
∆T2N (UDIMM) or ∆T2Q (RDIMM)
51
∆ T2P
52
∆ T3N
53
∆ T3P.fast
54
∆ T3P.slow
55
∆T4R / ∆T4R4W Sign
56
∆ T5B
57
∆ T7
58 Psi(ca) PLL
59 Psi(ca) REG
60
∆ TPLL
Data Sheet
Preliminary
2 GByte
1 GByte 1 GByte
512 MB
×72
×72
×72
×72
2 Ranks (×4) 1 Rank (×4) 2 Ranks (×8) 1 Rank (×8)
PC2–4300R–444
Rev. 1.1
Rev. 1.1 Rev. 1.1
Rev. 1.1
HEX
HEX
HEX
HEX
3C
3C
3C
3C
2D
2D
2D
2D
01
01
80
80
25
25
25
25
37
37
37
37
10
10
10
10
22
22
22
22
3C
3C
3C
3C
1E
1E
1E
1E
1E
1E
1E
1E
00
00
00
00
00
00
00
00
3C
3C
3C
3C
69
69
69
69
80
80
80
80
1E
1E
1E
1E
28
28
28
28
0F
0F
0F
0F
51
51
51
51
78
78
78
78
3E
3E
3E
3E
22
22
22
22
1E
1E
1E
1E
1E
1E
1E
1E
24
24
24
24
17
17
17
17
34
34
34
34
1E
1E
1E
1E
20
20
20
20
C4
C4
C4
C4
8C
8C
8C
8C
61
61
61
61
20
Rev. 0.85, 2004-04