HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
6.0 Serial Presence Detect Codes for Registered Modules
6.1 SPD Codes for PC2–4300R (–3.7)
Product Type
Organization
Label Code
Jedec SPD Revision
Byte# Description
0
Programmed SPD Bytes in EEPROM
1
Total number of Bytes in EEPROM
2
Memory Type (DDR2)
3
Number of Row Addresses
4
Number of Column Addresses
5
DIMM Rank and Stacking Information
6
Data Width
7
Not used
8
Interface Voltage Level
9
tCK @ CLmax (Byte 18) [ns]
10
tAC SDRAM @ CLmax (Byte 18) [ns]
11 Error Correction Support (non-ECC, ECC)
12 Refresh Rate and Type
13 Primary SDRAM Width
14 Error Checking SDRAM Width
15 Not used
16 Burst Length Supported
17 Number of Banks on SDRAM Device
18 Supported CAS Latencies
19 Not used
20 DIMM Type Information
21 DIMM Attributes
22 Component Attributes
23
tCK @ CLmax -1 (Byte 18) [ns]
24
tAC SDRAM @ CLmax -1 [ns]
25
tCK @ CLmax -2 (Byte 18) [ns]
26
tAC SDRAM @ CLmax -2 [ns]
27
tRP.min [ns]
28
tRRD.min [ns]
2 GByte
1 GByte 1 GByte
512 MB
×72
×72
×72
×72
2 Ranks (×4) 1 Rank (×4) 2 Ranks (×8) 1 Rank (×8)
PC2–4300R–444
Rev. 1.1
Rev. 1.1 Rev. 1.1
Rev. 1.1
HEX
HEX
HEX
HEX
80
80
80
80
08
08
08
08
08
08
08
08
0E
0E
0E
0E
0B
0B
0A
0A
61
60
61
60
48
48
48
48
00
00
00
00
05
05
05
05
3D
3D
3D
3D
50
50
50
50
02
02
02
02
82
82
82
82
04
04
08
08
04
04
08
08
00
00
00
00
0C
0C
0C
0C
04
04
04
04
38
38
38
38
00
00
00
00
01
01
01
01
07
05
05
04
01
01
01
01
3D
3D
3D
3D
50
50
50
50
50
50
50
50
60
60
60
60
3C
3C
3C
3C
1E
1E
1E
1E
Data Sheet
Preliminary
19
Rev. 0.85, 2004-04