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HYS64T64000GDL-5-C View Datasheet(PDF) - Infineon Technologies

Part Name
Description
MFG CO.
HYS64T64000GDL-5-C
Infineon
Infineon Technologies 
HYS64T64000GDL-5-C Datasheet PDF : 33 Pages
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HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
Symbol
Parameter
-5
DDR2-400
-3.7
DDR2-533
Unit
Min
Max
Min
Max
tRCD
Active to Read or Write delay (with and without Auto-Pre-
charge) delay
15
-
15
-
ns
tRP
tRRD
Precharge command period
Active bank A to Active bank
B command
x4 & x8
(1k page size)
15
-
15
-
ns
7.5
-
7.5
-
ns
tCCD
tWR
tDAL
tWTR
tRTP
tXARD
CAS A to CAS B Command Period
Write recovery time
Auto precharge write recovery + precharge time
Internal write to read command delay
Internal read to precharge command delay
Exit power down to any valid command
(other than NOP or Deselect)
2
-
2
-
tCK
15
-
15
-
ns
WR+tRP
-
WR+tRP
-
tCK
10
-
7.5
-
ns
7.5
-
7.5
-
ns
2
-
2
-
tCK
tXARDS
Exit active power-down mode to read command
(slew exit, lower power)
6 - AL
-
6 - AL
-
tCK
tXP
Exit precharge power-down to any valid command (other
than NOP or Deselect)
2
-
2
-
tCK
tXSRD Exit Self-Refresh to read command
200
-
200
-
tCK
tXSNR Exit Self-Refresh to non-read command
tRFC + 10
-
tRFC + 10
-
ns
tCKE CKE minimum high and low pulse width
3
-
3
-
tCK
tOIT OCD drive mode output delay
0
12
0
12
ns
tDELAY
Minimum time clocks remain ON after CKE asynchro-
nously drops low
tIS+tCK
+tIH
-
tIS+tCK
+tIH
-
ns
tREFI
Average Periodic Refresh
Interval
0oC - 85oC
85oC - 95oC
-
7.8
-
7.8
µs
-
3.9
-
3.9
1. For details and notes see the relevant INFINEON component datasheet
2. Timing definition and values for tis, tih, tds and tdh may change due to actual JEDEC work. This may also effect the SPD code
for these parameters.
5.2 ODT AC Electrical Characteristics and Operating Conditions (all speed bins)
Symbol Parameter / Condition
tAOND ODT turn-on delay
tAON ODT turn-on
DDR2-400/533
DDR2-667
tAONPD
tAOFD
tAOF
tAOFPD
tANPD
tAXPD
ODT turn-on (Power-Down Modes)
ODT turn-off delay
ODT turn-off
ODT turn-off delay (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
min.
2
tAC(min)
tAC(min)
tAC(min) + 2 ns
2.5
tAC(min)
tAC(min) + 2 ns
3
8
max.
Units
2
tCK
tAC(max) + 1 ns
ns
tAC(max) + 0.7 ns
2 tCK + tAC(max) + 1 ns ns
2.5
tCK
tAC(max) + 0.6 ns
ns
2.5 tCK + tAC(max) + 1 ns ns
-
tCK
-
tCK
Data Sheet
Preliminary
18
Rev. 0.85, 2004-04

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