Functional Block Diagram
VSS
Polarity
Blanking
Latch Enable
Data Input
Clock
32-Bit
Shift
Register
Data Out
Latch
Latch
Latch
Latch
HV4522/HV4622
HVOUT1
HVOUT2
(Outputs 3 to 30
not shown)
HVOUT31
HVOUT32
Function Table
Function
Data
Inputs
CLK
LE
BL
POL
All on
X
X
X
L
L
All off
X
X
X
L
H
Invert mode
X
X
L
H
L
Load S/R
Load
latches
Transparent
latch mode
H or L
↓
L
X
H or L
↑
X
H or L
↑
L
↓
H
H
↓
H
H
H
H
H
H
L
H
H
H
H
Notes:
H = high level = -12V, L = low level = 0V, X = irrelevant, ↓ = high-to-low transition, ↑ = low-to-high transition.
* = dependent on previous stage’s state before the last CLK high-to-low transition or last LE high.
Shift Reg
1 2…32
* *…*
* *…*
* *…*
H or L *…*
* *…*
* *…*
L *…*
H *…*
Outputs
HV Outputs
1 2…32
H H…H
L
L…L
*
*…*
*
*…*
*
*…*
*
*…*
L
*…*
H
*…*
Data Out
*
*
*
*
*
*
*
*
*
4