HT49CV7 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
HT49CV7 Datasheet PDF : 48 Pages
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HT49RV7/HT49CV7
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or an instruction clock
(system clock/4) or a real time clock oscillator (RTC os-
cillator). The timer is designed to prevent a software
malfunction or sequence from jumping to an unknown
location with unpredictable results. The WDT can be
disabled by options. But if the WDT is disabled, all exe-
cutions related to the WDT lead to no operation.
Once an internal WDT oscillator (RC oscillator with a pe-
riod of 65ms at 5V) is selected, it is divided by 212~215
(by configuration option to get the WDT time-out period).
The minimum WDT time-out period is 300ms~600ms.
This time-out period may vary with temperature, VDD
and process variations. By selecting the WDT configura-
tion option, longer time-out periods can be realized. If
the WDT time-out is selected, 215, the maximum
time-out period is divided by 215~216 which is 2.3s~4.7s.
If the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operates in the
same manner except that in the halt state the WDT may
stop counting and lose its protecting purposes. In this
situation the logic can only be restarted by external
logic. If the device operates in a noisy environment, us-
ing the on-chip RC oscillator (WDT OSC) is strongly rec-
ommended since the HALT will stop the system clock.
The WDT overflow under normal operation initializes a
²chip reset² and sets the status bit ²TO². In the HALT
mode, the overflow initializes a ²warm reset², and only
the Program Counter and SP are reset to zero. To clear
the contents of the WDT, there are three methods to be
adopted, i.e., external reset (a low level to RES), soft-
ware instruction, and a ²HALT² instruction. There are
two types of software instructions; ²CLR WDT² and the
other set - ²CLR WDT1² and ²CLR WDT2². Of these
two types of instruction, only one type of instruction can
be active at a time depending on the options - ²CLR
WDT² times selection option. If the ²CLR WDT² is se-
lected (i.e., CLR WDT times is equal to one), any execu-
tion of the ²CLR WDT² instruction clears the WDT. In the
case where the two ²CLR WDT1² and ²CLR WDT2² in-
structions are chosen (i.e., CLR WDT times is equal to
two), these two instructions have to be executed to clear
the WDT, otherwise, the WDT may reset the chip due to
time-out.
Multi-function Timer
The HT49RV7/HT49CV7 provides a multi-function timer
for the WDT, time base and RTC but with different
time-out periods. The multi-function timer consists of an
8-stage divider and a 7-bit prescaler, with the clock
source coming from the RTCC OSC or the instruction
clock (i.e., system clock divided by 4). The multi-function
timer also provides a selectable frequency signal (rang-
ing from fS/20 to fS/27) for the VFD driver circuits, and a
selectable frequency signal (ranging from fS/21 to fS/28)
for the buzzer output by options. It is recommended to
select a frequency as close as possible to 32kHz for the
VFD driver circuits to obtain good display clarity.
fS
D iv id e r
P r e s c a le r
R O M C o d e O p tio n
V F D D r iv e r ( fS /2 0 ~ fS /2 7 )
B u z z e r (fS /2 1~ fS /2 8)
Real Time Clock - RTC
The real time clock (RTC) is used to supply a regular in-
ternal interrupt. Its time-out period ranges from fS/28 to
fS/215 by software programming. Writing data to RT2,
RT1 and RT0 (bits 2, 1, 0 of RTCC; 09H) yields various
time-out periods. If the RTC time-out occurs and the in-
terrupt is enabled, the related interrupt request flag
(RTF; bit 1 of MFIS) is set and the multi-function inter-
rupt request flag (MFF; bit 6 of INTC1) is set. If the inter-
rupt (EMFI) is enabled, and the stack is not full, a
subroutine call to location 18H occurs.
RT2
0
0
0
0
1
1
1
1
RT1
0
0
1
1
0
0
1
1
RT0
0
1
0
1
0
1
0
1
RTC Clock Divided Factor
28*
29*
210*
211*
212
213
214
215
Note: * not recommended to be used
S y s te m C lo c k /4
R TC
O S C 32768H z
C o n fig u r a tio n fS
O p tio n
C o n fig u r a tio n fW D T
O p tio n
W
O
D
S
T
C
12kH
z
fW D T /2 8
D iv id e r
W DT
P r e s c a le r
M a s k O p tio n
W D T C le a r
Watchdog Timer
CK T
R
CK T
R
T im e - o u t R e s e t
2 15/fS ~ 2 16/fS
2 14/fS ~ 2 15/fS
2 13/fS ~ 2 14/fS
2 12/fS ~ 2 13/fS
Rev. 1.00
14
April 20, 2006
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