HT1380A/HT1381A
Timing Diagrams
Read Data Transfer
REST
S C LK
I/O
tC C
tC D H
tD C
0
7
C o m m a n d B y te
tC D D
0
O u tp u t D a ta B y te
tC D Z
7
Write Data Transfer
REST
S C LK
I/O
tC C
tC D H
tD C
0
tC L
7
C o m m a n d B y te
tC W H
tC H
tr
tC C H
tf
0
7
In p u t D a ta B y te
Application Circuit
V DD
M CU
In te r fa c e
C1 *
0 .1 m F
VDD
S C LK
X1
I/O
X2
REST
VSS
32768H z*
H T 1 3 8 0 A /H T 1 3 8 1 A
Note: * In order to obtain the correct frequency, it is recommended to use a crystal with a load capacitance of
9.0pF. It is not recommended to connect load capacitors to the X1 and X2 pins. If the power line is noisy, it
is recommended to add R1 and C1 for filtering out noise.
Rev. 1.00
9
June 15, 2012