AD14060(RevB) View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
AD14060 Datasheet PDF : 48 Pages
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AD14060/AD14060L
MEMORY WRITE—BUS MASTER
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN.
These specifications apply when the AD14060/AD14060L is the bus master accessing external memory space.
These switching characteristics also apply for bus master synchronous read/write timing (see the Synchronous Read/Write—Bus Master
section). If these timing requirements are met, the synchronous read/write timing can be ignored (and vice versa).
Table 9. Specifications
5V
3.3 V
Parameter
Min
Max
Min
Max
Unit
Timing Requirements:
tDAAK ACK Delay from Address, Selects1, 2
tDSAK ACK Delay from WR Low1
13.5 + 7 DT/8 + W
8 + DT/2 + W
13.5 + 7 DT/8 + W ns
8 + DT/2 + W
ns
Switching Characteristics:
tDAWH Address, Selects to WR
16.5 + 15 DT/16 + W
16.5 + 15 DT/16 + W
ns
De-asserted2
tDAWL Address, Selects to WR Low2
2.5 + 3 DT/8
2.5 + 3 DT/8
ns
tWW
WR Pulse Width
12 + 9 DT/16 + W
12 + 9 DT/16 + W
ns
tDDWH Data Setup before WR High
6.5 + DT/2 + W
6.5 + DT/2 + W
ns
tDWHA Address Hold after WR De-asserted 0 + DT/16 + H
0 + DT/16 + H
ns
tDATRWH Data Disable after WR De-asserted3 0.5 + DT/16 + H
6.5 + DT/16 + H 0.5 + DT/16 + H
6.5 + DT/16 + H ns
tWWR WR High to WR, RD, DMAGx Low 8 + 7 DT/16 + H
8 + 7 DT/16 + H
ns
tDDWR Data Disable before WR or RD Low 4.5 + 3 DT/8 + 1
4.5 + 3 DT/8 + 1
ns
tWDE WR Low to Data Enabled
−1.5 + DT/16
−1.5 + DT/16
ns
tSADADC Address, Selects to ADRCLK High2 −0.5 + DT/4
−0.5 + DT/4
ns
W = number of wait states specified in WAIT register × tCK.
H = tCK, if an address hold cycle occurs, as specified in WAIT register; otherwise, H = 0.
I = tCK, if a bus idle cycle occurs, as specified in WAIT register; otherwise, I = 0.
1 ACK delay/setup: User must meet tDAAK, tDSAK, or synchronous specification, tSACKC.
2 For MSx, SW, BMS, the falling edge is referenced.
3 See the System Hold Time Calculation Example section for the calculation of hold times given capacitive and dc loads.
ADDRESS
MSx, SW
BMS
WR
DATA
ACK
RD, DMAG
ADRCLK
(OUT)
tDAWL
tDAWH
tWDE
tWW
tDDWH
tDAAK
tDSAK
tSADADC
Figure 8. Memory Write—Bus Master
tDWHA
tWWR
tDATRWH
tDDWR
Rev. B | Page 9 of 48
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