HIP6015 View Datasheet(PDF) - Intersil
Part Name
Description
MFG CO.
HIP6015 Datasheet PDF : 12 Pages
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HIP6015
Output Voltage Program
The output voltage of a HIP6015 converter is programmed to
discrete levels between 1.8VDC and 3.5VDC. The voltage
identification (VID) pins program an internal voltage
reference (DACOUT) with a TTL-compatible 5-bit
digital-to-analog converter (DAC). The level of DACOUT also
sets the PGOOD and OVP thresholds. Table 1 specifies the
DACOUT voltage for the 32 different combinations of
connections on the VID pins. The output voltage should not
be adjusted while the converter is delivering power. Remove
input power before changing the output voltage. Adjusting
the output voltage during operation could toggle the PGOOD
signal and exercise the overvoltage protection.
All VID pin combinations resulting in a 0V output setting
activate the Power-On Reset function and disable the gate
drive circuitry. For these specific VID combinations, though,
PGOOD asserts a high level. This unusual behavior has
been implemented in order to allow for operation in dual-
microprocessor systems by AND-ing the PGOOD signals
from the two individual power converters.
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to
another can generate voltage transients across the
impedances of the interconnecting bond wires and circuit
traces. These interconnecting impedances should be
minimized by using wide, short printed circuit traces. The
critical components should be located as close together as
possible using ground plane construction or single point
grounding.
VIN
HIP6015
UGATE
PHASE
Q1
LO VOUT
CIN
CO
D2
Figure 5 shows the critical power components of the
converter. To minimize the voltage overshoot the
interconnecting wires indicated by heavy lines should be
part of ground or power plane in a printed circuit board. The
components shown in Figure 6 should be located as close
together as possible. Please note that the capacitors CIN
and CO each represent numerous physical capacitors.
Locate the HIP6015 within 3 inches of the MOSFET, Q1. The
circuit traces for the MOSFET’s gate and source connections
from the HIP6015 must be sized to handle up to 1A peak
current.
Figure 6 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS PIN and locate the capacitor, Css
close to the SS pin because the internal current source is
only 10µA. Provide local VCC decoupling between VCC and
GND pins. Locate the capacitor, CBOOT as close as practical
to the BOOT and PHASE pins.
BOOT
D1
CBOOT
HIP6015
PHASE
SS
VCC +12V
+VIN
Q1 LO
D2 CO
VOUT
CSS
GND
CVCC
FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
Feedback Compensation
Figure 7 highlights the voltage-mode control loop for a buck
converter. The output voltage (VOUT) is regulated to the
Reference voltage level. The error amplifier (Error Amp)
output (VE/A) is compared with the oscillator (OSC)
triangular wave to provide a pulse-width modulated (PWM)
wave with an amplitude of VIN at the PHASE node. The
PWM wave is smoothed by the output filter (LO and CO).
RETURN
FIGURE 5. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
7
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