HIP6015 View Datasheet(PDF) - Intersil
Part Name
Description
MFG CO.
HIP6015 Datasheet PDF : 12 Pages
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HIP6015
the largest component of power dissipation for the MOSFET.
Switching losses also contribute to the overall MOSFET
power loss (see the equations below). These equations
assume linear voltage-current transitions and are
approximations. The gate-charge losses are dissipated by the
HIP6015 and do not heat the MOSFET. However, large gate-
charge increases the switching interval, tSW, which increases
the upper MOSFET switching losses. Ensure that the
MOSFET is within its maximum junction temperature at high
ambient temperature by calculating the temperature rise
according to package thermal-resistance specifications. A
separate heatsink may be necessary depending upon
MOSFET power, package type, ambient temperature and air
flow.
PCOND = IO2 • rDS(ON) • D
PSW = 1/2 IO • VIN • tSW • FS
Where: D is the duty cycle = VOUT / VIN,
tSW is the switching interval, and
FS is the switching frequency.
Standard-gate MOSFETs are normally recommended for
use with the HIP6015. However, logic-level gate MOSFETs
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFET’s absolute
gate-to-source voltage rating determine whether logic-level
MOSFETs are appropriate.
Figure 9 shows the upper gate drive (BOOT pin) supplied by
a bootstrap circuit from VCC. The boot capacitor, CBOOT,
develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of VCC
less the boot diode drop (VD) when the Schottky diode, D2,
conducts. Logic-level MOSFETs can only be used if the
MOSFET’s absolute gate-to-source voltage rating exceeds
the maximum voltage applied to VCC.
Figure 10 shows the upper gate drive supplied by a direct
connection to VCC. This option should only be used in
converter systems where the main input voltage is +5VDC or
less. The peak upper gate-to-source voltage is approximately
VCC less the input supply. For +5V main power and +12VDC
for the bias, the gate-to-source voltage of Q1 is 7V. A
logic-level MOSFET is a good choice for Q1 under these
conditions.
+12V
VCC
HIP6015
-
+
DBOOT
+ VD -
+5V OR +12
BOOT
UGATE
PHASE
CBOOT
Q1
VG-S ≈ VCC - VD
D2
GND
FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION
+12V
VCC
HIP6015
-
+
BOOT
UGATE
PHASE
GND
+5V OR LESS
Q1
D2
NOTE:
VG-S ≈ VCC -5V
IGURE 10. UPPER GATE DRIVE - DIRECT VCC DRIVE OPTION
Schottky Selection
Rectifier D2 conducts when the upper MOSFET Q1 is off. The
diode should be a Schottky type for low power losses. The
power dissipation in the Schottky rectifier is approximated by:
PCOND = I0 x Vf x (1 - D)
Where: D is the duty cycle = VOUT / VIN, and
Vf is the Schottky forward voltage drop
In addition to power dissipation, package selection and
heatsink requirements are the main design tradeoffs in
choosing the Schottky rectifier. Since the three factors are
interrelated, the selection process is an iterative procedure.
The maximum junction temperature of the rectifier must
remain below the manufacturer’s specified value, typically
125oC. By using the package thermal resistance
specification and the schottky power dissipation equation
(shown above), the junction temperature of the rectifier can
be estimated. Be sure to use the available airflow and
ambient temperature to determine the junction temperature
rise.
10
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