HDD-1206 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
HDD-1206 Datasheet PDF : 4 Pages
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THEORY OF OPERATION
The equivalent circuit for the for the HDD-1206 D/A converter
CURRENT.OUTPUT DrA CONVERTERS
A brief reviewof the salient characteristicsof current DrAcon-
is shown in functional block diagram.
The unit consisTSof input registers, fast-SCHIIDgcurrent
verters may be a useful approach to
of the HDP-1206 unit.
the operation
DII\, output amplifier, timing generntor, aDd ass{ICiared
OiA converters are inherently fa$lcr than
The purpose of the input register circuits is to de-skew the
inpUt bits and assure Their simultaneous arrival at the inpul of
The curren! O/A. This is critkal b<."C3usteime skew on the input
data bils is a major contributor to discontinuities, or
"
voltage-output types hecausc of ttIe absence of an
This mean$
converters have no slew rate limi-
tation which can slow settling; not are Theysubject to the overshoot
and
problems often associated with feedback
in the analog output of a OIA.
Bmh current-switching and
converters display a
The Timing Generator includes a Track & Hold circuit and
discontinuity, or "glitch," in their
output$ because of the
generates the required internal pulses for operation whenever it
basic characteristic of satUrated logit: (rrL is an example) which
receives a Strobe input pulse. See
I, t.he HOO.1206
causes the
delay to be less for negal
OBSOL- LETE timing diagrnm.
"T'
STRO6t
1+,
HLGi$IER
HOW
TRACK
1
1
I
MTAoX .. -I I J ~OSAlCM!!iAI..Sr I
ROLIt
olm""
Figure 1, HDD-1206 TimIng DIagram (DIgital Inputs not
Cfumgfng!
As shown, the Strobe pulse is a positive-going 1'1'1. pulse supplied
by the user of the HPO-1206. Internal timing circuits establish
than il is for
inputs.
This difference in propagation
manifests itself as a "worst
case
at the major C'arrypoint. or mid-scale, of the OUtpUI
range of the .::urrent converte" This is the
at which nearly
equal and opposite .::urrems arc being switched within the
converter.
The "glilch" at mid-scale, the switching point of the Most
Bil (MSB), will be halved at the !I. and 3;'
halved again at The and %
etc, The
of the
is a function si2nal dynamks and caonot
The variations in
caused
dynamics
create a multitUde of illlermodulation (1M) products, some of
which fall imo the video
as 1>purious
and
increased noise level. These 1.\1
arc also relatively
immune to elimination by
The amplitude of the glitch can be reduced by
bits; bur no amount of dc-skewing or
the
can negate
the maximum 55ns delay from the leading edge of the Strobe
the physics nf sarurated logic which cause Ihe glitch to be
pulse to the leading edge of the T/H (TrackiHold)
and
initially.
the maximum IOns dclay from the
edge of the
pulse to the leading edge of the Register pulse. The data from
Ihe input
are strobed int.o the current D/A at the end
of Ihis 6Sm interval, so must be valid by that tinle.
The heS!
then, is to cause the glitch to remain a constant
across the entire outpUt range of the converter. The efficiencies
of Ihe circuit will be enhanced if the solUtion can also permit
the full drive capabilities of the currcnt-outpul DiA in
The user determincs the width of the T/H pulse (and the Register
either unipolar or bipolar modes of
pul~e) by select.ing the value of the RUDLDresistor. St'C
The design approach used in the Analog Devices HDP-1206
I and 2. As shown, the width uf the Hold pulse can vary from
approximatcly 30ns to approximately lOOnsby using resistOr
DiA converter accomplishes these desired goals and
voltage OUtpUtsat bigh update rates.
values from Ik 10 5k, respectivel)'.
NOTES ON OEGLlTCHING
Refer again to the equivalent circuit for the HDD-1206. The
data bits are applied thmugh the input register to the current.out-
put PIA converter, which is capable of
up to 5.l2mA
of ~'\!IpUtcurrent.
The oUtput of the currern D/.'\, in rum, is applied to the
~
of the OUtput
via
external 10 the HDD-1206.
The Timing Generator supplies the necessary
and
to apply signals to the current D/A and OUTputamplifier after
the initial glitch caused by the digital inpUts has subsided.
Figure 2, Hold TIme vs. RHolD
For most applications, a value of 3.6kH and a pulse width of
approximately 85ns is the optimum choke, This pulse width
wiIJ "hold" the analo~ oUtpUt of the HDD-1206 OiA uOli! the
"glileh" resulting from the most recent update has passed.
without infringing on Ihe word rate capabilitie$ of the
HPP-1206.
The digital "I" (Hold) level of the TIH pulse CaOSC$the switch
at the input Qf the amplifier to open, holding the last value uf
tbe current DlA con\'erter. During this hold inten'al,
transients c;wsed by updating digital inputs arc masked from
the amplifier, thereby avoiding HDD-1206 output discontinuities
whose amplitUde would be a function of signal
Ten nanoseconds after the 'fiH pulse goes ({)the
"I"
the register pulse also changes stare frum "0" tQ "I".
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