GS1560ACF(2007) View Datasheet(PDF) - Gennum -> Semtech
Part Name
Description
MFG CO.
GS1560ACF Datasheet PDF : 80 Pages
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GS1560A/GS1561 Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type Description
14
15, 17
16
18
19
20
21
CD2
DDI2, DDI2
TERM2
SMPTE_BYPASS
RSET
NC
CD_VDD
NC
SDO_EN/DIS
NC
Non
Synchronous
Analog
Analog
Non
Synchronous
Analog
–
–
–
Non
Synchronous
–
Input
Input
Input
Input /
Output
Input
–
Power
–
Input
–
STATUS SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the presence of a serial digital input signal. Normally
generated by a Gennum automatic cable equalizer.
When LOW, the serial digital input signal received at the DDI2 and DDI2
pins is considered valid.
When HIGH, the associated serial digital input signal is considered to be
invalid. In this case, the LOCKED signal is set LOW and all parallel outputs
are muted.
Differential input pair for serial digital input 2.
Termination for serial digital input 2. AC couple to PDBUFF_GND.
CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
This pin will be an input set by the application layer in slave mode, and will
be an output set by the device in master mode.
Master Mode (MASTER/SLAVE = HIGH)
The SMPTE_BYPASS signal will be HIGH only when the device has
locked to a SMPTE compliant data stream. It will be LOW otherwise.
Slave Mode (MASTER/SLAVE = LOW)
When set HIGH in conjunction with DVB_ASI = LOW, the device will be
configured to operate in SMPTE mode. All I/O processing features may be
enabled in this mode.
When set LOW, the device will not support the descrambling, decoding or
word alignment of received SMPTE data. No I/O processing features will
be available.
GS1560A
Used to set the serial digital loop-through output signal amplitude. Connect
to CD_VDD through 281Ω +/- 1% for 800mVp-p single-ended output swing.
GS1561
No Connect.
GS1560A
Power supply connection for the serial digital cable driver. Connect to
+1.8V DC analog.
GS1561
No Connect.
GS1560A
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable the serial digital output loop-through stage.
When set LOW, the serial digital output signals SDO and SDO are
disabled and become high impedance.
When set HIGH, the serial digital output signals SDO and SDO are
enabled.
GS1561
No Connect.
27360 - 10 January 2007
10 of 80
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