FM93C56TL View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
MFG CO.
FM93C56TL
Fairchild Semiconductor
FM93C56TL Datasheet PDF : 16 Pages
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Timing Diagrams (Continued)
WRITE ENABLE CYCLE (WEN)
PRE
PE
tCS
CS
SK
1 0 0 A7 A6
A1 A0
DI
Start Opcode
Address
Bit Bits(2)
Bits(8)
High - Z
DO
93CS56:
Address bits pattern -> 1-1-x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1)
WRITE DISABLE CYCLE (WDS)
PRE ;;;;;;;;;;;;;;;;;;;;;;;;;;;
PE ;;;;;;;;;;;;;;;;;;;;;;;;;;;
tCS
CS
SK
1 0 0 A7 A6
A1 A0
DI
Start Opcode
Address
Bit Bits(2)
Bits(8)
High - Z
DO
93CS56:
Address bits pattern -> 0-0-x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1)
WRITE CYCLE (WRITE)
PRE
PE
tCS
CS
SK
1 0 1 A7 A6
A1 A0 D15 D14
D1 D0
DI
Start Opcode
Address
Data
tWP
Bit Bits(2)
Bits(8)
Bits(16)
DO
High - Z
Ready
Busy
93CS56:
Address bits pattern -> x-A6-A5-A4-A3-A2-A1-A0; (x -> Don't Care, can be 0 or 1); ( A6-A0 -> User defined )
Data bits pattern -> User defined
FM93CS56 Rev. C.1
10
www.fairchildsemi.com
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