FAN5078D3MPX View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
MFG CO.
FAN5078D3MPX Datasheet PDF : 18 Pages
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PGOOD Signal
PGOOD monitors the status of the PWM output and VTT.
PGOOD remains LOW unless all these conditions are met:
SS is above 3.5V
Fault latch is cleared
FB is between 90% and 110% of VREF
VTT is in regulation.
Protection
The converter output is monitored and protected against
extreme overload, short-circuit, over-voltage, and under-
voltage conditions.
An internal fault latch is set for any fault intended to shut
down the IC. When the fault latch is set, the IC discharges its
output by driving LDRV HIGH until VDDQ IN < 0.5V. LDRV
goes LOW until VDDQ IN > 0.8V. This discharges VDDQ
without causing undershoot (negative output voltage).
To discharge the output capacitors, a 40Ω load resistor is
switched from VDDQ IN to PGND whenever the IC is in fault
condition or when EN is LOW. After a latched fault, operation
can be restored by recycling power or toggling the EN pin.
Under-Voltage Shutdown
If FB stays below the under-voltage threshold for 2μs, the
fault latch is set. This fault is prevented from setting the fault
latch during PWM soft-start (SS < 1.3V).
Over-Current Sensing
If the circuit’s current limit signal (ILIM det shown in Figure
11) is high at the beginning of a clock cycle, a pulse-skipping
circuit is activated and HDRV is inhibited. The circuit
continues to pulse skip in this manner for the next 8 clock
cycles. If, at any time from the 9th to the 16th clock cycle, the
ILIM det is again reached, the fault latch is set. If ILIM det
does not occur between cycle 9 and 16, normal operation is
restored and the over-current circuit resets itself.
This fault is prevented from setting the fault latch during soft-
start (SS < 1.3V).
OVP / HS Fault / FB Short to GND Detection
A HS fault is detected when there is more than 0.5V from
SW to PGND 350ns after LDRV reaches 4V (same as the
current sampling time).
OVP fault detection occurs if FB>115% VREF for 16 clock cycles.
During soft-start, the output voltage could potentially "run
away" if either the FB pin is shorted to GND or R1 is open.
This fault is detected if the following condition persists for
more than 14μs during soft-start:
VDDQ IN (PWM output voltage) > 1V
FB < 100mV
Any of these faults sets the fault latch, even during the SS
time (SS < 1.2V).
To ensure that FB pin open does not cause a destructive
condition, a 1.3μA current source ensures that the FB pin is
HIGH if open. This causes the regulator to keep the output
LOW and eventually results in an under-voltage fault
shutdown (after PWM SS completes).
COMP
FB
SS
1.3μA
ISS
–
+ E/A
+
VREF
ISNS
RAMP
–
+ PWM
+
Figure 15. SS Clamp and FB Open Protection
Over-Temperature Protection
The chip incorporates an over-temperature protection circuit
that shuts the chip down when a die temperature of ~150°C
is reached. Normal operation is restored when the die
temperature falls below 125°C with internal Power On Reset
asserted, resulting in a full soft-start cycle. To accomplish this,
the over-temperature comparator discharges the SS pin.
VTT Regulator Section (see Figure 3)
The VTT regulator includes an internal resistor divider (50K
for each resistor) from the output of the PWM regulator. If
the REF IN pin is left open, the divider produces a voltage
50% of VDDQ IN. Using a low-impedance external precision
voltage divider produces greater accuracy.
The VTT regulator is enabled when S3#I is HIGH and the
PWM regulator’s internal PGOOD signal is true. The VTT
regulator also includes its own PGOOD signal, which is
HIGH when VTT SNS > 90% of REF IN.
Figure 14. Over-Current Protection Waveforms
© 2008 Fairchild Semiconductor Corporation
15
FAN5078D3 • Rev. 1.0.0
www.fairchildsemi.com
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