FAN5078D3MPX View Datasheet(PDF) - Fairchild Semiconductor

Part Name

Description

MFG CO.

FAN5078D3MPX

Complete ACPI Compliant Power Solution for DDR3 Memory System

Fairchild Semiconductor 

5V SB

V(UVLO)

SS

4V

3.8V

1V

VDDQ

3.3V LDO

T0

T1

T2

T3 T4 T5

Figure 9. Start-up Sequence into S0

PWM Regulator

A PSPICE model and spreadsheet calculator are available

in Application Note AN-6006 for the VDDQ PWM regulator

to select external components and verify loop stability. The

topics covered below provide the explanation behind the

calculations in the spreadsheet.

Setting the Output Voltage

The output voltage of the PWM regulator can be set in the

range of 0.9V to 80% of its power input by an external

resistor divider.

The internal reference is 0.9V. The output is divided down

by an external voltage divider to the FB pin (for example,

R1 and R2 in Figure 1). There is also a 1.3μA current

sourced out of FB to ensure that if the pin is open, VDDQ

remains LOW. The output voltage therefore is:

0.9V = VOUT − 0.9V + 1.3μA

(3a)

R2

R1

To minimize noise pickup on this node, keep the resistor

to GND (R2) below 2K. In the example below, R2 is 1.82K

and R1 is calculated:

R1 = R2 • (VOUT − 0.9) =

0.9 − 1.3μA

(3b)

1.815K ≈ 1.82K

The synchronous buck converter is optimized for 5V input

operation. The PWM modulator uses an average current

mode control for simplified feedback loop compensation.

Oscillator

The oscillator frequency is 300Khz. The internal PWM

ramp is reset on the rising clock edge.

PWM Soft Start

When the PWM regulator is enabled, the circuit waits until

the VDDQ IN pin is below 100mV to ensure that the soft-

start cycle does not begin with a large residual voltage on

the PWM regulator output.

When the PWM regulator is disabled, 40Ω is connected

from VDDQ IN to PGND to discharge the output. The

circuit waits until the FB pin is below 100mV to ensure that

the soft-start cycle does not begin with a large residual

voltage on the VDDQ regulator output.

The voltage at the positive input of the error amplifier is

limited to VCSS, which is charged with about 45μA. Once

CSS reaches 0.9V, the output voltage is in regulation.

The time it takes SS to reach 0.9V and VDDQ to achieve

regulation is:

T0.9

≈

0.9

X CSS

45

(4)

where T0.9 is in ms if CSS is in nF.

CSS charges another 400mV before the PWM regulator’s

fault latch is enabled. When CSS reaches 1.2V, the VTT

regulator begins its soft-start. After VTT is in regulation,

PGOOD is allowed to go HIGH (open).

© 2008 Fairchild Semiconductor Corporation

12

FAN5078D3 • Rev. 1.0.0

www.fairchildsemi.com

Share Link: