AD7322BRU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
AD7322BRU Datasheet PDF : 18 Pages
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AD7322
Preliminary Technical Data
When the ADC starts a conversion (Figure 5), SW2 will open
and SW1 will move to position B, causing the comparator to
become unbalanced. The control logic and the charge
redistribution DAC is used to add and subtract fixed amounts
of charge from the sampling capacitor arrays to bring the
comparator back into a balanced condition. When the
comparator is rebalanced, the conversion is complete. The
Control Logic generates the ADC output code.
Vin0
B
CS
A SW1
CAPACITIVE
DAC
COMPARATOR
SW2
CONTROL
LOGIC
AGND
Figure 5. ADC Conversion Phase(Single Ended)
Figure 6 shows the differential configuration during the
Acquisition phase. For the Conversion Phase, SW3 will open,
SW1 and SW2 will move to position B, see Figure 7. The output
impedances of the source driving the Vin+ and Vin- pins must
be matched; otherwise the two inputs will have different settling
times, resulting in errors.
Vin+
Vin-
B
CS
A SW1
A SW2
B
CS
VREF
CAPACITIVE
DAC
COMPARATOR
SW3
CONTROL
LOGIC
CAPACITIVE
DAC
Figure 6. ADC Differential Configuration during Acquisition Phase
Vin+
Vin-
B
CS
A SW1
A SW2
B
CS
VREF
CAPACITIVE
DAC
COMPARATOR
SW3
CONTROL
LOGIC
CAPACITIVE
DAC
Figure 7. ADC Differential Configuration during Conversion Phase
Output Coding
The AD7322 default output coding is set to two’s complement.
The output coding is controlled by the Coding bit in the
Control Register. To change the output coding to Straight
Binary Coding the Coding bit in the Control Register must be
set. When operating in Sequence mode the output coding for
each channel in the sequence will be the value written to the
coding bit during the last write to the Control Register.
Transfer Functions
The designed code transitions occur at successive integer LSB
values (i.e., 1 LSB, 2 LSB, and so on). The LSB size is dependant
on the Analog input Range selected.
Table 6. LSB sizes for each Analog Input Range
Input Range Full Scale Range/4096 LSB Size
±10V
20V/4096
4.882 mV
±5V
10V/4096
2.441 mV
±2.5V
5V/4096
1.22 mV
0 to 10V
10V/4096
2.441 mV
The ideal transfer characteristic for the AD7322 when Twos
Complement coding is selected is shown in Figure 8, and the
ideal transfer characteristic for the AD7322 when Straight
Binary coding is selected is shown in Figure 9.
011...111
011...110
000...001
000...000
111...111
100...010
100...001
100...000
-FSR/2 + 1LSB
+FSR/2 - 1LSB
VREF - 1LSB
ANALOG INPUT
Figure 8. Twos Complement Transfer Characteristic (Bipolar Ranges)
111...111
111...110
111...000
011...111
000...010
000...001
000...000
1LSB
-FSR/2
FSR/2 -1LSB
ANALOG INPUT
Figure 9. Straight Binary Transfer Characteristic (Bipolar Ranges)
ANALOG INPUT
The analog inputs of the AD7322 may be configured as Single-
Ended, True differential or Pseudo Differential via the Control
Register Mode Bits as shown in Table 9 of the Register Section.
The AD7322 can accept True bipolar input signals. On power
up the Analog inputs will operate as 2 Single-Ended Analog
Input Channels. If True Differential or Pseudo Differential is
required, a write to the Control register is necessary to change
this configuration after power up.
Figure 10 shows the equivalent Analog input circuit of the
AD7322 in Single-Ended Mode. Figure 11 shows the equivalent
Analog input structure in Differential mode. The Two Diodes
provide ESD protection for the Analog Inputs.
Rev. PrE | Page 10 of 18
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