EL4584CS View Datasheet(PDF) - Intersil

Part Name

Description

MFG CO.

EL4584CS

Horizontal Genlock, 4FSC

Intersil 

Timing Diagrams

EL4584

Falling edge of HSYNC + 110ns locks

to rising edge of Ext Div signal.

FIGURE 1. PLL LOCKED CONDITION (PHASE ERROR = 0)

θE = (Tθ/TH) × 360°

TH = HSYNC period

Tθ = phase error period

FIGURE 2. OUT OF LOCK CONDITION

FIGURE 3. TEST CIRCUIT 1

5

FN7174.2

July 25, 2005

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