AD7829BR View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
AD7829BR Datasheet PDF : 28 Pages
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AD7822/AD7825/AD7829
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
DB2 1
20 DB3
DB1 2
19 DB4
DB0 3
18 DB5
CONVST 4
17 DB6
CS 5 AD7822 16 DB7
RD
6
TOP VIEW
(Not to Scale)
15 AGND
DGND 7
14 VDD
EOC 8
13 VREF IN/OUT
PD 9
12 VMID
NC 10
11 VIN1
NC = NO CONNECT
Figure 3. Pin Configuration
DB2 1
24 DB3
DB1 2
23 DB4
DB0 3
22 DB5
CONVST 4
21 DB6
CS 5 AD7825 20 DB7
RD 6 TOP VIEW 19 AGND
(Not to Scale)
DGND 7
18 VDD
EOC 8
17 VREF IN/OUT
A1 9
16 VMID
A0 10
15 VIN1
PD 11
14 VIN2
VIN4 12
13 VIN3
Figure 4. Pin Configuration
DB2 1
DB1 2
DB0 3
CONVST 4
CS 5
RD 6
DGND 7
EOC 8
A2 9
A1 10
A0 11
VIN8 12
VIN7 13
VIN6 14
AD7829
TOP VIEW
(Not to Scale)
28 DB3
27 DB4
26 DB5
25 DB6
24 DB7
23 AGND
22 VDD
21 VREF IN/OUT
20 VMID
19 VIN1
18 VIN2
17 VIN3
16 VIN4
15 VIN5
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Mnemonic Description
VIN1 to VIN8
VDD
Analog Input Channels. The AD7822 has a single input channel; the AD7825 and AD7829 have four and eight analog input
channels, respectively. The inputs have an input span of 2.5 V and 2 V depending on the supply voltage (VDD). This span can
be centered anywhere in the range AGND to VDD using the VMID pin. The default input range (VMID unconnected) is AGND to
2 V (VDD = 3 V ± 10%) or AGND to 2.5 V (VDD = 5 V ± 10%). See the Analog Input section of the data sheet for more information.
Positive Supply Voltage, 3 V ± 10% and 5 V ± 10%.
AGND
Analog Ground. Ground reference for track-and-hold, comparators, reference circuit, and multiplexer.
DGND
Digital Ground. Ground reference for digital circuitry.
CONVST
Logic Input Signal. The convert start signal initiates an 8-bit analog-to-digital conversion on the falling edge of this signal. The
falling edge of this signal places the track-and-hold in hold mode. The track-and-hold goes into track mode again 120 ns after
the start of a conversion. The state of the CONVST signal is checked at the end of a conversion. If it is logic low, the AD7822/
AD7825/AD7829 powers down (see the Operating Modes section of the data sheet).
EOC
Logic Output. The end-of-conversion signal indicates when a conversion has finished. The signal can be used to interrupt
a microcontroller when a conversion has finished or latch data into a gate array (see the Parallel Interface section).
CS
Logic Input Signal. The chip select signal is used to enable the parallel port of the AD7822/AD7825/AD7829. This is necessary
if the ADC is sharing a common data bus with another device.
PD
Logic Input. The power-down pin is present on the AD7822 and AD7825 only. Bringing the PD pin low places the AD7822 and
AD7825 in power-down mode. The ADCs power up when PD is brought logic high again.
RD
Logic Input Signal. The read signal is used to take the output buffers out of their high impedance state and drive data onto
the data bus. The signal is internally gated with the CS signal. Both RD and CS must be logic low to enable the data bus.
A0 to A2
Channel Address Inputs. The address of the next multiplexer channel must be present on these inputs when the RD signal
goes low.
DB0 to DB7 Data Output Lines. They are normally held in a high impedance state. Data is driven onto the data bus when both RD and CS
go active low.
VREF IN/OUT
Analog Input and Output. An external reference can be connected to the AD7822/AD7825/AD7829 at this pin. The on-chip
reference is also available at this pin. When using the internal reference, this pin can be left unconnected or, in some cases, it
can be decoupled to AGND with a 0.1 μF capacitor.
VMID
The VMID pin, if connected, is used to center the analog input span anywhere in the range of AGND to VDD (see the Analog
Input section).
Rev. C | Page 7 of 28
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