AD7822BRUZ1 View Datasheet(PDF) - Analog Devices

Part Name

Description

MFG CO.

AD7822BRUZ1

3 V/5 V, 2 MSPS, 8-Bit, 1-/4-/8-Channel Sampling ADCs

Analog Devices 

A suggestion is to tie CONVST to VDD or DGND through a pull-up

or pull-down resistor. A rising edge on the CONVST pin causes

the AD7829 to fully power up, while a rising edge on the PD pin

causes the AD7822 and AD7825 to fully power up. For applica-

tions where power consumption is of concern, the automatic

power-down at the end of a conversion should be used to improve

power performance (see the Power vs. Throughput section).

SUPPLY

4.5V TO 5.5V

10µF

1.25V TO

3.75V INPUT

0.1µF

2.5V

AD780

PARALLEL

INTERFACE

VDD

VREF

VMID

DB0 TO DB7

VIN1

EOC

VIN24

AD7822/

AD7825/

RD

AD7829

CS

VIN4(VIN85)

AGND

CONVST

A01

A11

DGND

A22

PD3

µC/µP

1A0, A1

2A2

3PD

4VIN2 TO VIN4

5VIN5 TO VIN8

AD7825/AD7829

AD7829

AD7822/AD7825

AD7825/AD7829

AD7829

Figure 9. Typical Connection Diagram

ADC TRANSFER FUNCTION

The output coding of the AD7822/AD7825/AD7829 is straight

binary. The designed code transitions occur at successive integer

LSB values (that is, 1 LSB, 2 LSBs, and so on). The LSB size =

VREF/256 (VDD = 5 V) or the LSB size = (0.8 VREF)/256 (VDD =

3 V). The ideal transfer characteristic for the AD7822/AD7825/

AD7829 is shown in Figure 10.

11111111

111...110

(VDD = 5V)

1LSB = VREF/256

111...000

10000000

000...111

(VDD = 3V)

1LSB = 0.8VREF/256

000...010

000...001

00000000

1LSB

VMID

(VDD = 5V) VMID – 1.25V

(VDD = 3V) VMID – 1V

VMID + 1.25V – 1LSB

VMID + 1V – 1LSB

ANALOG INPUT VOLTAGE

Figure 10. Transfer Characteristic

AD7822/AD7825/AD7829

ANALOG INPUT

The AD7822 has a single input channel, and the AD7825 and

AD7829 have four and eight input channels, respectively. Each

input channel has an input span of 2.5 V or 2.0 V, depending on

the supply voltage (VDD). This input span is automatically set up

by an on-chip VDD detector circuit. A 5 V operation of the ADCs

is detected when VDD exceeds 4.1 V, and a 3 V operation is

detected when VDD falls below 3.8 V. This circuit also possesses

a degree of glitch rejection; for example, a glitch from 5.5 V to

2.7 V up to 60 ns wide does not trip the VDD detector.

The VMID pin is used to center this input span anywhere in the

range of AGND to VDD. If no input voltage is applied to VMID,

the default input range is AGND to 2.0 V (VDD = 3 V ± 10%),

that is, centered about 1.0 V; or AGND to 2.5 V (VDD = 5 V ±

10%), that is, centered about 1.25 V. When using the default

input range, the VMID pin can be left unconnected, or in some

cases, it can be decoupled to AGND with a 0.1 μF capacitor.

If, however, an external VMID is applied, the analog input range

is from VMID − 1.0 V to VMID + 1.0 V (VDD = 3 V ± 10%), or

from VMID − 1.25 V to VMID + 1.25 V (VDD = 5 V ± 10%).

The range of values of VMID that can be applied depends on the

value of VDD. For VDD = 3 V ± 10%, the range of values that can

be applied to VMID is from 1.0 V to VDD − 1.0 V and from 1.25 V to

VDD − 1.25 V when VDD = 5 V ± 10%. Table 5 shows the relevant

ranges of VMID and the input span for various values of VDD.

Figure 11 illustrates the input signal range available with various

values of VMID.

Table 5.

VMID

VMID Ext

VMID Ext

VDD Internal Max

VIN Span Min

VIN Span Unit

5.5 1.25

4.25

3.0 to 5.5 1.25

0 to 2.5 V

5.0 1.25

3.75

2.5 to 5.0 1.25

0 to 2.5 V

4.5 1.25

3.25

2.0 to 4.5 1.25

0 to 2.5 V

3.3 1.00

2.3

1.3 to 3.3 1.00

0 to 2.0 V

3.0 1.00

2.0

1.0 to 3.0 1.00

0 to 2.0 V

2.7 1.00

1.7

0.7 to 2.7 1.00

0 to 2.0 V

Rev. C | Page 11 of 28

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