EDE1104AASE View Datasheet(PDF) - Elpida Memory, Inc
Part Name
Description
MFG CO.
EDE1104AASE Datasheet PDF : 65 Pages
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EDE1104AASE, EDE1108AASE
Pin Function
CK, /CK (input pins)
CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the
positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK
(both directions of crossing).
/CS (input pin)
All commands are masked when /CS is registered high. /CS provides for external rank selection on systems with
multiple ranks. /CS is considered part of the command code.
/RAS, /CAS, /WE (input pins)
/RAS, /CAS and /WE (along with /CS) define the command being entered.
A0 to A13 (input pins)
Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write
commands to select one location out of the memory array in the respective bank. The address inputs also provide
the op-code during mode register set commands.
[Address Pins Table]
Part number
EDE1104AASE
EDE1108AASE
Address (A0 to A13)
Row address
AX0 to AX13
AX0 to AX13
Column address
AY0 to AY9, AY11
AY0 to AY9
Notes
A10 (AP) (input pin)
A10 is sampled during a precharge command to determine whether the precharge applies to one bank (A10 = low)
or all banks (A10 = high). If only one bank is to be precharged, the bank is selected by BA0, BA1 and BA2.
BA0, BA1, BA2 (input pins)
BA0, BA1 and BA2 define to which bank an active, read, write or precharge command is being applied. BA0 also
determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle.
[Bank Select Signal Table]
BA0
BA1
BA2
Bank 0
L
L
L
Bank 1
H
L
L
Bank 2
L
H
L
Bank 3
H
H
L
Bank 4
L
L
H
Bank 5
H
L
H
Bank 6
L
H
H
Bank 7
H
H
H
Remark: H: VIH. L: VIL.
Data Sheet E0404E20 (Ver. 2.0)
16
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