DS83C530-ENL View Datasheet(PDF) - Maxim Integrated
Part Name
Description
MFG CO.
DS83C530-ENL Datasheet PDF : 45 Pages
| |||
DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
PIN DESCRIPTION (continued)
PIN
PLCC TQFP
NAME
FUNCTION
30
23
P2.0 (AD8) Port 2 (A8–A15), I/O. Port 2 is a bidirectional I/O port. The reset condition of
31
24
P2.1 (AD9) Port 2 is logic high. In this state, a weak pullup holds the port high. This condition
also serves as an input mode, since any external circuit that writes to the port will
32
25
P2.2 (AD10) overcome the weak pullup. When software writes a 0 to any port pin, the device
33
26
P2.3 (AD11) will activate a strong pulldown that remains on until either a 1 is written or a reset
occurs. Writing a 1 after the port has been at 0 will cause a strong transition driver
34
27
P2.4 (AD12) to turn on, followed by a weaker sustaining pullup. Once the momentary strong
35
28
P2.5 (AD13) driver turns off, the port again becomes both the output high and input state. As an
alternate function Port 2 can function as MSB of the external address bus. This
36
29
P2.6 (AD14) bus can be used to read external ROM and read/write external RAM memory or
37
30
P2.7 (AD15) peripherals.
15
8
16
9
17
10
18
11
19
12
20
13
21
14
22
15
P3.0
Port 3, I/O. Port 3 functions as both an 8-bit, bi-directional I/O port and an
alternate functional interface for external interrupts, Serial Port 0, Timer 0 and 1
Inputs, and RD and WR strobes. The reset condition of Port 3 is with all bits at a
P3.1
logic 1. In this state, a weak pullup holds the port high. This condition also serves
as an input mode, since any external circuit that writes to the port will overcome
P3.2
the weak pullup. When software writes a 0 to any port pin, the device will activate
a strong pulldown that remains on until either a 1 is written or a reset occurs.
Writing a 1 after the port has been at 0 will cause a strong transition driver to turn
P3.3
on, followed by a weaker sustaining pullup. Once the momentary strong driver
turns off, the port again becomes both the output high and input state. The
alternate modes of Port 3 are outlined below.
P3.4
Port Alternate
Function
P3.0 RXD0
Serial Port 0 Input
P3.5
P3.1 TXD0
P3.2 INT0
P3.3 INT1
Serial Port 0 Output
External Interrupt 0
External Interrupt 1
P3.6
P3.4 T0
Timer 0 External Input
P3.5 T1
P3.6 WR
P3.7
P3.7 RD
Timer 1 External Input
External Data Memory Write Strobe
External Data Memory Read Strobe
42
35
51
44
27
20
28
21
2, 11, 13,
14, 40,
41
4, 6, 7,
33, 34,
47
EA
VBAT
RTCX2
RTCX1
N.C.
External Access Input, Active Low. Connect to ground to use an external ROM.
Internal RAM is still accessible as determined by register settings. Connect to VCC
to use internal ROM.
VBAT Input. Connect to the power source that maintains SRAM and RTC when
VCC < VBAT. Can be connected to a 3V lithium battery or a super cap. Connect to
GND if battery will not be used with device.
Timekeeping Crystals. A 32.768kHz crystal between these pins supplies the time
base for the RTC. The devices support both 6pF and 12.5pF load capacitance
crystals as selected by an SFR bit (described later). To prevent noise from
affecting the RTC, the RTCX2 and RTCX1 pins should be guard-ringed with
GND2.
Not Connected. These pins should not be connected. They are reserved for use
with future devices in the family.
6 of 45
Share Link: 