DS2156 View Datasheet(PDF) - Maxim Integrated

Part Name

Description

MFG CO.

DS2156

T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface

Maxim Integrated 

DS2156

36.3 Receive-Side AC Characteristics

AC CHARACTERISTICS: RECEIVE SIDE

(Figure 36-8, Figure 36-9, and Figure 36-10)

(VDD = 3.3V ±5%, TA = 0°C to +70°C for DS2156L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS2156LN.)

PARAMETER

RCLKO Period

RCLKO Pulse Width

RCLKO Pulse Width

RCLKI Period

RCLKI Pulse Width

SYMBOL CONDITIONS MIN

tLP

tLH

(Note 1)

200

tLL

(Note 1)

200

tLH

(Note 2)

150

tLL

(Note 2)

150

tCP

tCH

20

tCL

20

(Note 3)

TYP

488 (E1)

648 (T1)

0.5 tLP

0.5 tLP

0.5 tLP

0.5 tLP

488 (E1)

648 (T1)

0.5 tCP

0.5 tCP

648

MAX

UNITS

ns

ns

ns

ns

ns

RSYSCLK Period

(Note 4)

tSP

(Note 5)

(Note 6)

488

ns

244

ns

122

(Note 7)

RSYSCLK Pulse Width

tSH

tSL

RSYNC Setup to RSYSCLK Falling

tSU

RSYNC Pulse Width

tPW

RPOSI/RNEGI Setup to RCLKI Falling

tSU

RPOSI/RNEGI Hold From RCLKI

Falling

tHD

RSYSCLK, RCLKI Rise and Fall Times

tR, tF

Delay RCLKO to RPOSO, RNEGO Valid

tDD

Delay RCLK to RSER, RDATA, RSIG,

RLINK Valid

tD1

Delay RCLK to RCHCLK, RSYNC,

RCHBLK, RFSYNC, RLCLK

tD2

Delay RSYSCLK to RSER, RSIG Valid

tD3

Delay RSYSCLK to RCHCLK,

RCHBLK, RMSYNC, RSYNC

tD4

61

20

0.5 tSP

ns

20

0.5 tSP

ns

20

ns

50

ns

20

ns

20

ns

22

ns

50

ns

50

ns

50

ns

22

ns

22

ns

Note 1: Jitter attenuator enabled in the receive path.

Note 2: Jitter attenuator disabled or enabled in the transmit path.

Note 3: RSYSCLK = 1.544MHz

Note 4: RSYSCLK = 2.048MHz

Note 5: RSYSCLK = 4.096MHz

Note 6: RSYSCLK = 8.192MHz

Note 7: RSYSCLK = 16.384MHz

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