4. DS21Q42 REGISTER MAP
Register Map Sorted by Address Table 4-1
ADDRESS
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
W
–
R/W
–
–
–
–
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R
R
R
R
R
R
R/W
REGISTER NAME
HDLC Control
HDLC Status
HDLC Interrupt Mask
Receive HDLC Information
Receive Bit Oriented Code
Receive HDLC FIFO
Transmit HDLC Information
Transmit Bit Oriented Code
Transmit HDLC FIFO
Not used
Common Control 7
Not used
Not used
Not used
Not used
Device ID
Receive Information 3
Common Control 4
In–Band Code Control
Transmit Code Definition
Receive Up Code Definition
Receive Down Code Definition
Transmit Channel Control 1
Transmit Channel Control 2
Transmit Channel Control 3
Common Control 5
Transmit DS0 Monitor
Receive Channel Control 1
Receive Channel Control 2
Receive Channel Control 3
Common Control 6
Receive DS0 Monitor
Status 1
Status 2
Receive Information 1
Line Code Violation Count 1
Line Code Violation Count 2
Path Code Violation Count 1
Path Code violation Count 2
Multiframe Out of Sync Count 2
Receive FDL Register
Receive FDL Match 1
22 of 119
DS21Q42
REGISTER
ABBREVIATION
HCR
HSR
HIMR
RHIR
RBOC
RHFR
THIR
TBOC
THFR
(set to 00H)
CCR7
(set to 00H)
(set to 00H)
(set to 00H)
(set to 00H)
IDR
RIR3
CCR4
IBCC
TCD
RUPCD
RDNCD
TCC1
TCC2
TCC3
CCR5
TDS0M
RCC1
RCC2
RCC3
CCR6
RDS0M
SR1
SR2
RIR1
LCVCR1
CVCR2
PCVCR1
PCVCR2
MOSCR2
RFDL
RMTCH1