DS21Q42
Signal Name: JTRST*
Signal Description: IEEE 1149.1 Test Reset
Signal Type: Input
This signal is used to asynchronously reset the test access port controller. At power up, JTRST* must be
set low and then high. This action will set the device into the DEVICE ID mode allowing normal device
operation. If boundary scan is not used and FMS = 0, this pin should be held low. This function is
available when FMS = 0. When FMS=1, this pin is held LOW internally. This pin is pulled up internally
by a 10K ohm resistor.
Signal Name: JTMS
Signal Description: IEEE 1149.1 Test Mode Select
Signal Type: Input
This pin is sampled on the rising edge of JTCLK and is used to place the test port into the various defined
IEEE 1149.1 states. This pin is pulled up internally by a 10K ohm resistor. If not used, this pin should be
left unconnected. This function is available when FMS = 0.
Signal Name: JTCLK
Signal Description: IEEE 1149.1 Test Clock Signal
Signal Type: Input
This signal is used to shift data into JTDI pin on the rising edge and out of JTDO pin on the falling edge.
If not used, this pin should be connected to VSS. This function is available when FMS = 0.
Signal Name: JTDI
Signal Description: IEEE 1149.1 Test Data Input
Signal Type: Input
Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin is pulled up
internally by a 10K ohm resistor. If not used, this pin should be left unconnected. This function is
available when FMS = 0.
Signal Name: JTDO
Signal Description: IEEE 1149.1 Test Data Output
Signal Type: Output
Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin
should be left unconnected. This function is available when FMS = 0.
SUPPLY PINS
Signal Name: VDD
Signal Description: Positive Supply
Signal Type: Supply
2.97 to 3.63 volts.
Signal Name: VSS
Signal Description: Signal Ground
Signal Type: Supply
0.0 volts.
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