DPA426GN View Datasheet(PDF) - Power Integrations, Inc
Part Name
Description
MFG CO.
DPA426GN
Power Integrations, Inc
DPA426GN Datasheet PDF : 34 Pages
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DPA422-426
+VIN
36 - 57 VDC
J1-1
C1
1 µF
100 V
-VIN
J1-2
R1
1 MΩ
1%
C2
47 pF
200 V
VR1
SMAJ
150A
1 T1 9, 10
L1
1 µH, 2A
R2
2
619 kΩ
1%
D2
SL43
C5
330 µF
6V
C6
330 µF
6V
6, 7
4
C7
330 µF
6V
3
R5
D3
100 Ω BAV19, SOD323
5
DPA-Switch
D
L
U1
CONTROL DPA423G
C
S
XF
C3
0.1 µF
R3
50 V
8.66 kΩ
1%
R4
5.1 Ω
C4
22 µF
10 V
C8
1 µF
50 V
R6
51 Ω
U2
PC357
C10
0.33 µF
U3
CAT431L,
SOT23
R7
1 kΩ R8
34 kΩ
1%
C11
0.1 µF
R9
20 kΩ
1%
3.3 V, 2 A
C9
1 µF
10 V
J2-1
RTN
J2-2
PI-3806-061704
Figure 26. A Cost Effective 6.6 W, 3.3 V Flyback DC-DC Converter.
Output regulation is achieved by using secondary side voltage
reference, U3. The resistor divider formed by R10 and R11,
together with the reference voltage, determines the output
voltage. Diode D3 and C13 form a soft-finish network that,
together with the internal duty cycle and current limit soft-start
of the DPA‑Switch, prevent output overshoot at start-up.
Resistor R7 ensures that the soft-finish capacitor is discharged
quickly when the output falls out of regulation. Control loop
response is shaped by R6, C16, R12, C14, R9, R4 and C5,
providing a wide bandwidth and good phase margin at gain
crossover. Since the PWM control in DPA-Switch is voltage mode,
no slope compensation is required for duty cycles above 50%.
Cost Effective 6.6 W Flyback Converter
The DPA-Switch flyback power supply provides a cost effective
solution for high density PoE and VoIP DC-DC applications.
Figure 26 shows a typical implementation of a single output
flyback converter using the DPA423G. For applications that
require input to output isolation, this simple, low component
count design delivers 6.6 W at 3.3 V from a 36 VDC to 57 VDC
input with a nominal efficiency at 48 VDC of 80%.
Resistor R2 programs the input undervoltage and overvoltage
thresholds to 33 V and 86 V respectively. Resistors R1 and R3
program the internal device current limit. The addition of line
sense resistor R1 reduces the current limit with increasing input
voltage, preventing excessive overload output current. In this
design the overload output current varies less than ±2.5%
across the entire input voltage range. Controlling the current
limit also reduces secondary component stress and leakage
inductance spikes, allowing the use of a lower VRRM (30 V rather
than 40 V) Schottky output diode, D2.
The primary side Zener clamp VR1 ensures the peak drain
voltage is kept below the 220 V BVDSS rating of U1 under input
surge and overvoltage events. During normal operation, VR1
does not conduct and C2 is sufficient to limit the peak drain
voltage.
The primary bias winding provides CONTROL pin current after
start-up. Diode D3 rectifies the bias winding, while components
R5 and C8 reduce high frequency switching noise and prevent
peak charging of the bias voltage. Capacitor C3 provides local
decoupling of U1 and should be physically close to the
CONTROL and SOURCE pins. Energy storage for start-up and
auto-restart timing is provided by C4.
The secondary is rectified by D2 and the Low ESR tantalum
output capacitors, C5-C7, minimizing switching ripple and
maximizing efficiency. A small footprint secondary output choke
L1 and ceramic output capacitor C9 are adequate to reduce
high frequency noise and ripple to below 35 mV peak-peak
under full load conditions.
The output voltage is sensed by the voltage divider formed by
resistors R8 and R9 and is fed to the low voltage 1.24 V
reference U3. Feedback compensation is provided by R6, R7
and C11 together with C4 and R4. Capacitor C10 provides a
soft-finish characteristic, preventing output overshoot during
start-up.
Low Cost PoE VoIP Phone Converter
The basic circuitry to support IEEE standard 802.3af Power
over Ethernet (PoE) is straightforward. Class 0 signature and
classification circuits can be implemented with a single resistor
and the required undervoltage lockout function is a voltage
www.powerint.com
15
Rev. T 12/12
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