
Function Table
(Each Flip-Flop)
Inputs
Clear
Clock
D
L
X
X
H
↑
H
H
↑
L
H
L
X
H = HIGH Level (steady state)
L = LOW Level (steady state)
X = Don’t Care
↑ = Transition from LOW-to-HIGH level
Q0 = The level of Q before the indicated steady-state input conditions were established.
† = DM74LS175 only
Logic Diagrams
Outputs
Q
Q†
L
H
H
L
L
H
Q0
Q0
DM74LS174
DM74LS175
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