DM74AS280 View Datasheet(PDF) - Fairchild Semiconductor

Part Name

Description

MFG CO.

DM74AS280

9-Bit Parity Generator/Checker

Fairchild Semiconductor 

Typical Applications

Three DM74AS280s can be used to implement a 25-line

parity generator/checker.

As an alternative, the outputs of two or three parity genera-

tors/checkers can be decoded with a 2-input (AS86) or 3-

input (S135) exclusive-OR gate for 18 or 27-line parity

applications.

Longer word lengths can be implemented by cascading

DM74AS280s. As shown in Figure 2, parity can be gener-

ated for word lengths up to 81 bits.

FIGURE 1. 25-Line

Parity/Generator Checker

www.fairchildsemi.com

FIGURE 2. 81-Line Parity/Generator Checker

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